Infineon TRAVEO T2G - 19.1.8 CH 7; 19.1.9 CH 8; 19.1.10 CH 9; 19.1.11 CH 10

Technical Reference Manual 002-29852 Rev. *B
Register Name Address Permission Description
PASS0_SAR0_CH6_TR_CTL
0x40900980 FULL Trigger control.
PASS0_SAR0_CH6_SAMPLE_CTL
0x40900984 FULL Sample control.
PASS0_SAR0_CH6_POST_CTL
0x40900988 FULL Post processing control
PASS0_SAR0_CH6_RANGE_CTL
0x4090098C FULL Range thresholds
PASS0_SAR0_CH6_INTR
0x40900990 FULL Interrupt request register.
PASS0_SAR0_CH6_INTR_SET
0x40900994 FULL Interrupt set request register
PASS0_SAR0_CH6_INTR_MASK
0x40900998 FULL Interrupt mask register.
PASS0_SAR0_CH6_INTR_MASKED
0x4090099C FULL Interrupt masked request register
PASS0_SAR0_CH6_WORK
0x409009A0 FULL Working data register
PASS0_SAR0_CH6_RESULT
0x409009A4 FULL Result data register
PASS0_SAR0_CH6_GRP_STAT
0x409009A8 FULL Group status register
PASS0_SAR0_CH6_ENABLE
0x409009B8 FULL Enable register
PASS0_SAR0_CH6_TR_CMD
0x409009BC FULL Software triggers
19.1.8 CH 7
Register Name Address Permission Description
PASS0_SAR0_CH7_TR_CTL
0x409009C0 FULL Trigger control.
PASS0_SAR0_CH7_SAMPLE_CTL
0x409009C4 FULL Sample control.
PASS0_SAR0_CH7_POST_CTL
0x409009C8 FULL Post processing control
PASS0_SAR0_CH7_RANGE_CTL
0x409009CC FULL Range thresholds
PASS0_SAR0_CH7_INTR
0x409009D0 FULL Interrupt request register.
PASS0_SAR0_CH7_INTR_SET
0x409009D4 FULL Interrupt set request register
PASS0_SAR0_CH7_INTR_MASK
0x409009D8 FULL Interrupt mask register.
PASS0_SAR0_CH7_INTR_MASKED
0x409009DC FULL Interrupt masked request register
PASS0_SAR0_CH7_WORK
0x409009E0 FULL Working data register
PASS0_SAR0_CH7_RESULT
0x409009E4 FULL Result data register
PASS0_SAR0_CH7_GRP_STAT
0x409009E8 FULL Group status register
PASS0_SAR0_CH7_ENABLE
0x409009F8 FULL Enable register
PASS0_SAR0_CH7_TR_CMD
0x409009FC FULL Software triggers
19.1.9 CH 8
Register Name Address Permission Description
PASS0_SAR0_CH8_TR_CTL
0x40900A00 FULL Trigger control.
PASS0_SAR0_CH8_SAMPLE_CTL
0x40900A04 FULL Sample control.
PASS0_SAR0_CH8_POST_CTL
0x40900A08 FULL Post processing control
PASS0_SAR0_CH8_RANGE_CTL
0x40900A0C FULL Range thresholds
PASS0_SAR0_CH8_INTR
0x40900A10 FULL Interrupt request register.
PASS0_SAR0_CH8_INTR_SET
0x40900A14 FULL Interrupt set request register
PASS0_SAR0_CH8_INTR_MASK
0x40900A18 FULL Interrupt mask register.
PASS0_SAR0_CH8_INTR_MASKED
0x40900A1C FULL Interrupt masked request register
PASS0_SAR0_CH8_WORK
0x40900A20 FULL Working data register
PASS0_SAR0_CH8_RESULT
0x40900A24 FULL Result data register
PASS0_SAR0_CH8_GRP_STAT
0x40900A28 FULL Group status register
PASS0_SAR0_CH8_ENABLE
0x40900A38 FULL Enable register
PASS0_SAR0_CH8_TR_CMD
0x40900A3C FULL Software triggers
19.1.10 CH 9
Register Name Address Permission Description
PASS0_SAR0_CH9_TR_CTL
0x40900A40 FULL Trigger control.
PASS0_SAR0_CH9_SAMPLE_CTL
0x40900A44 FULL Sample control.
PASS0_SAR0_CH9_POST_CTL
0x40900A48 FULL Post processing control
PASS0_SAR0_CH9_RANGE_CTL
0x40900A4C FULL Range thresholds
PASS0_SAR0_CH9_INTR
0x40900A50 FULL Interrupt request register.
PASS0_SAR0_CH9_INTR_SET
0x40900A54 FULL Interrupt set request register
PASS0_SAR0_CH9_INTR_MASK
0x40900A58 FULL Interrupt mask register.
PASS0_SAR0_CH9_INTR_MASKED
0x40900A5C FULL Interrupt masked request register
PASS0_SAR0_CH9_WORK
0x40900A60 FULL Working data register
PASS0_SAR0_CH9_RESULT
0x40900A64 FULL Result data register
PASS0_SAR0_CH9_GRP_STAT
0x40900A68 FULL Group status register
PASS0_SAR0_CH9_ENABLE
0x40900A78 FULL Enable register
PASS0_SAR0_CH9_TR_CMD
0x40900A7C FULL Software triggers
19.1.11 CH 10
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers