Infineon TRAVEO T2G - 5.1.37 CPUSS_ROM_CTL

Technical Reference Manual 002-29852 Rev. *B
5.1.37 CPUSS_ROM_CTL
Description:
ROM control
Address:
0x402013C4
Offset:
0x13C4
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x1
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:2] SLOW_WS [1:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:10] FAST_WS [9:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:1 SLOW_WS RW R 1 Memory wait states for the slow clock domain
('clk_slow'). The number of wait states is expressed in
'clk_hf' clock domain cycles.
Timing paths to and from the memory have a (fixed)
minimum duration that always needs to be
considered/met. The 'clk_hf' clock domain frequency
determines this field's value such that the timing paths
minimum duration is met. A table/formula will be
provided for this field's values for different 'clk_hf'
frequencies.
8:9 FAST_WS RW R 0 Memory wait states for the fast clock domain
('clk_fast'). The number of wait states is expressed in
'clk_hf' clock domain cycles.
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2022-04-18
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