Infineon TRAVEO T2G - 26.8.39 RES_CAUSE

Technical Reference Manual 002-29852 Rev. *B
26.8.39 RES_CAUSE
Description:
Reset Cause Observation Register
Address:
0x40261800
Offset:
0x1800
Retention:
Retained
IsDeepSleep:
Yes
Comment:
Indicates the cause for reset(s) that occurred in the system. All bits in this register assert when
the corresponding reset cause occurs and must be cleared by firmware. Low-voltage cause
bits are reset whenever the low-voltage supply is initialized, including XRES, POR, brown-out,
and during Hibernate wakeup. HT products also clear low-voltage cause bits for over-voltage,
over-current, and WDT resets. Refer to the reset source documentation to understand what
reset source behavior for different configuration or modes.
Default:
0x40000000
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name RESET
_MCWDT2
[7:7]
RESET
_MCWDT1
[6:6]
RESET
_MCWDT0
[5:5]
RESET
_SOFT [4:4]
RESET_TC
_
DBGRESET
[3:3]
RESET
_DPSLP
_FAULT
[2:2]
RESET
_ACT
_FAULT
[1:1]
RESET
_WDT [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:9] RESET
_MCWDT3
[8:8]
Bits 23 22 21 20 19 18 17 16
Name RESET
_OCD_ACT
_LINREG
[23:23]
RESET
_OVD
VCCD
[22:22]
RESET
_OVD
VDDA
[21:21]
RESET
_OVD
VDDD
[20:20]
RESET
_BOD
VCCD
[19:19]
RESET
_BOD
VDDA
[18:18]
RESET
_BOD
VDDD
[17:17]
RESET
_XRES
[16:16]
Bits 31 30 29 28 27 26 25 24
Name None
[31:31]
RESET
_POR
VDDD
[30:30]
RESET
_STRUCT
_XRES
[29:29]
RESET
_PXRES
[28:28]
None
[27:27]
RESET
_PMIC
[26:26]
RESET
_OCD
_REGHC
[25:25]
RESET
_OCD
_DPSLP
_LINREG
[24:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 RESET_WDT RW1C A 0 A basic WatchDog Timer (WDT) reset has occurred
since last power cycle. ULP products: This is a low-
voltage cause bit that hardware clears when the low-
voltage supply is initialized (see comments above).
For products that support high-voltage cause
detection, this bit blocks recording of other high-
voltage cause bits, except RESET_PORVDDD.
Hardware clears this bit during POR. This bit is not
blocked by other HV cause bits.
1 RESET_ACT_FAULT RW1C A 0 Fault logging system requested a reset from its Active
logic. This is a low-voltage cause bit that hardware
clears when the low-voltage supply is initialized (see
comments above).
2 RESET_DPSLP_FAULT RW1C A 0 Fault logging system requested a reset from its
DeepSleep logic. This is a low-voltage cause bit that
hardware clears when the low-voltage supply is
initialized (see comments above).
1683
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers