Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
3 RESET_TC_DBGRESET RW1C A 0 Test controller or debugger asserted reset. Only resets
debug domain. This is a low-voltage cause bit that
hardware clears when the low-voltage supply is
initialized (see comments above).
4 RESET_SOFT RW1C A 0 A CPU requested a system reset through it's
SYSRESETREQ. This can be done via a debugger
probe or in firmware. This is a low-voltage cause bit
that hardware clears when the low-voltage supply is
initialized (see comments above).
5 RESET_MCWDT0 RW1C A 0 Multi-Counter Watchdog timer reset #0. This is a low-
voltage cause bit that hardware clears when the low-
voltage supply is initialized (see comments above).
6 RESET_MCWDT1 RW1C A 0 Multi-Counter Watchdog timer reset #1. This is a low-
voltage cause bit that hardware clears when the low-
voltage supply is initialized (see comments above).
7 RESET_MCWDT2 RW1C A 0 Multi-Counter Watchdog timer reset #2. This is a low-
voltage cause bit that hardware clears when the low-
voltage supply is initialized (see comments above).
8 RESET_MCWDT3 RW1C A 0 Multi-Counter Watchdog timer reset #3. This is a low-
voltage cause bit that hardware clears when the low-
voltage supply is initialized (see comments above).
16 RESET_XRES RW1C A 0 External XRES pin was asserted. This is a high-
voltage cause bit that blocks recording of other high-
voltage cause bits, except RESET_PORVDDD.
Hardware clears this bit during POR. This bit is not
blocked by other HV cause bits.
17 RESET_BODVDDD RW1C A 0 External VDDD supply crossed brown-out limit. Note
that this cause will only be observable as long as the
VDDD supply does not go below the POR (power on
reset) detection limit. Below this limit it is not possible
to reliably retain information in the device. This is a
high-voltage cause bit that blocks recording of other
high-voltage cause bits, except RESET_PORVDDD.
Hardware clears this bit during POR.
18 RESET_BODVDDA RW1C A 0 External VDDA supply crossed the brown-out limit.
This is a high-voltage cause bit that blocks recording of
other high-voltage cause bits, except
RESET_PORVDDD. Hardware clears this bit during
POR.
19 RESET_BODVCCD RW1C A 0 Internal VCCD core supply crossed the brown-out limit.
Note that this detector will detect gross issues with the
internal core supply, but may not catch all brown-out
conditions. Functional and timing supervision (CSV,
WDT) is provided to create fully failsafe internal crash
detection. This is a high-voltage cause bit that blocks
recording of other high-voltage cause bits, except
RESET_PORVDDD. Hardware clears this bit during
POR.
20 RESET_OVDVDDD RW1C A 0 Overvoltage detection on the external VDDD supply.
This is a high-voltage cause bit that blocks recording of
other high-voltage cause bits, except
RESET_PORVDDD. Hardware clears this bit during
POR.
21 RESET_OVDVDDA RW1C A 0 Overvoltage detection on the external VDDA supply.
This is a high-voltage cause bit that blocks recording of
other high-voltage cause bits, except
RESET_PORVDDD. Hardware clears this bit during
POR.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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