Infineon TRAVEO T2G - 26.8.43 PWR_TRIM_WAKE_CTL

Technical Reference Manual 002-29852 Rev. *B
26.8.43 PWR_TRIM_WAKE_CTL
Description:
Wakeup Trim Register
Address:
0x40263008
Offset:
0x3008
Retention:
Retained
IsDeepSleep:
Yes
Comment:
Trim bits for DEEPSLEEP wakeup.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name WAKE_DELAY [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 WAKE_DELAY RW R 0 Wakeup holdoff specifies the number of IMO cycles for
power system settling before continuing the wakeup
sequence. Fastest wakeup is achieved by using the
smallest number allowed for the product.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers