Infineon TRAVEO T2G - 9.3.7 DW_ACT_DESCR_Y_CTL

Technical Reference Manual 002-29852 Rev. *B
9.3.7 DW_ACT_DESCR_Y_CTL
Description:
Active descriptor Y loop control
Address:
0x40280034
Offset:
0x34
Retention:
Not Retained
IsDeepSleep:
No
Comment:
If the currently active descriptor has not Y_CTL register, this MMIO register provides
undefined information.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name DATA [7:0]
Bits 15 14 13 12 11 10 9 8
Name DATA [15:8]
Bits 23 22 21 20 19 18 17 16
Name DATA [23:16]
Bits 31 30 29 28 27 26 25 24
Name DATA [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 DATA R W Undefined Copy of DESCR_Y_CTL of the currently active
descriptor.
[11:0] SRC_Y_INCR
Specifies increment of source address for each Y loop
iteration (in multiples of SRC_TRANSFER_SIZE). This
field is a signed number in the range [-2048, 2047].
[23:12] DST_Y_INCR
Specifies increment of destination address for each Y
loop iteration (in multiples of DST_TRANSFER_SIZE).
This field is a signed number in the range [-2048,
2047].
[31:24] Y_COUNT
Number of iterations (minus 1) of the 'Y loop'
(X_COUNT+1)*(Y_COUNT+1) is the number of single
transfers in a 2D transfer). This field is an unsigned
number in the range [0, 255], representing 1 through
256 iterations.
For single, 1D and CRC transfer descriptor types,
descriptor will not have Y_CTL.
868
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers