Infineon TRAVEO T2G - 22.5 Register Details; 22.5.1 SMPU; 22.5.1.1 PROT_SMPU_MS0_CTL

Technical Reference Manual 002-29852 Rev. *B
22.5 Register Details
22.5.1 SMPU
22.5.1.1 PROT_SMPU_MS0_CTL
Description:
Master 0 protection context control
Address:
0x40230000
Offset:
0x0
Retention:
Retained
IsDeepSleep:
No
Comment:
Each master has an associated SMPU MS_CTL register. This register provides master
specific information. In a system with a secure entity, this register is typically only accessible
by the secure entity, to prevent a master from changing its own privileged setting, security
setting, arbitration priority or enabled protection contexts.
Master 0 (CM0+ processor) uses SMPU MS0_CTL.
Master 1 (cryptography IP) uses SMPU MS1_CTL.
Master 2 (DataWire 0) uses SMPU MS2_CTL.
Master 3 (DataWire 1) uses SMPU MS3_CTL.
....
Master 14 (CM4 processor) uses SMPU MS14_CTL.
Master 15 (test controller) uses SMPU MS15_CTL.
Default:
0x303
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:2] NS [1:1] P [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:10] PRIO [9:8]
Bits 23 22 21 20 19 18 17 16
Name PC_MASK
_0 [16:16]
Bits 31 30 29 28 27 26 25 24
Name PC_MASK_15_TO_1 [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 P RW R 1 Privileged setting ('0': user mode; '1': privileged mode).
Notes:
This field is ONLY used for masters that do NOT
provide their own user/privileged access control
attribute.
The default/reset field value provides privileged mode
access capabilities.
1 NS RW R 1 Security setting ('0': secure mode; '1': non-secure
mode).
Notes:
This field is ONLY used for masters that do NOT
provide their own secure/non-secure access control
attribute.
Note that the default/reset field value provides non-
secure mode access capabilities to all masters.
1320
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers