Infineon TRAVEO T2G - 14.2.12 FLASHC_CM0_CA_STATUS0

Technical Reference Manual 002-29852 Rev. *B
14.2.12 FLASHC_CM0_CA_STATUS0
Description:
CM0+ cache status 0
Address:
0x40240440
Offset:
0x440
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name VALID32 [7:0]
Bits 15 14 13 12 11 10 9 8
Name VALID32 [15:8]
Bits 23 22 21 20 19 18 17 16
Name VALID32 [23:16]
Bits 31 30 29 28 27 26 25 24
Name VALID32 [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 VALID32 R W 0 Sixteen valid bits of the cache line specified by
CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR.
949
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers