Infineon TRAVEO T2G - 4.13.1.4 CM4_ITM_TCR

Technical Reference Manual 002-29852 Rev. *B
4.13.1.4 CM4_ITM_TCR
Description:
Trace Control Register
Address:
0xE0000E80
Offset:
0xE80
Retention:
Retained
IsDeepSleep:
No
Comment:
The ITM_TCR characteristics are:
Purpose: Configures and controls transfers through the ITM interface.
Usage constraints: For information about constraints that apply in a system that supports
multiple trace streams
see CoreSight requirements for the TraceBusID field on page C1-778.
Configurations: Always implemented.
Attributes: See Table C1-11 on Arm TRM page C1-773, and the register field descriptions.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:5] SWOENA
[4:4]
TXENA
[3:3]
SYNCENA
[2:2]
TSENA
[1:1]
ITMENA
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:12] GTSFREQ [11:10] TSPRESCALE [9:8]
Bits 23 22 21 20 19 18 17 16
Name BUSY
[23:23]
TRACEBUSID [22:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0 ITMENA RW R 0 Enables the ITM:
0 Disabled.
1 Enabled.
This is the master enable for the ITM unit. A debugger
must set this bit to 1 to permit writes to all Stimulus
Port registers.
A Power-on reset clears this bit to 0.
1 TSENA RW R 0 Enables Local timestamp generation:
0 Disabled.
1 Enabled.
A Power-on reset clears this bit to 0.
2 SYNCENA RW R 0 Enables Synchronization packet transmission for a
synchronous TPIU:
0 Disabled.
1 Enabled.
A Power-on reset clears this bit to 0.
Note: If a debugger sets this bit to 1 it must also
configure DWT_CTRL.SYNCTAP for the correct
synchronization speed, see Control register,
DWT_CTRL on Arm TRM page C1-797.
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2022-04-18
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