Infineon TRAVEO T2G - 13.5.1.7 FAULT_STRUCT_MASK0

Technical Reference Manual 002-29852 Rev. *B
13.5.1.7 FAULT_STRUCT_MASK0
Description:
Fault mask 0
Address:
0x40210050
Offset:
0x50
Retention:
Retained
IsDeepSleep:
No
Comment:
The MASK0, MASK1, MASK2 registers specify 'enables' for fault sources. Only 'enabled' fault
sources will be captured by this fault structure (and result in STATUS.VALID and INTR.FAULT
being set to '1'). When a fault source is captured, its corresponding bit field in PENDING0/1/2
is set to '0'.
When multiple fault structures are present and the mask fields of the fault structures overlap
(the same source is 'enabled' for multiple fault structures), an overlapping enabled pending
fault source is captured by a single fault structure that has not captured a fault (the fault
structure with the lowest index has precedence).
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name SOURCE [7:0]
Bits 15 14 13 12 11 10 9 8
Name SOURCE [15:8]
Bits 23 22 21 20 19 18 17 16
Name SOURCE [23:16]
Bits 31 30 29 28 27 26 25 24
Name SOURCE [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 SOURCE RW R 0 Fault source enables:
Bits 31-0: Fault sources 31 to 0.
928
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers