Infineon TRAVEO T2G - 23.9.27 SCB_RX_FIFO_RD

Technical Reference Manual 002-29852 Rev. *B
23.9.27 SCB_RX_FIFO_RD
Description:
Receiver FIFO read
Address:
0x40600340
Offset:
0x340
Retention:
Not Retained
IsDeepSleep:
No
Comment:
When the IP is disabled (CTRL.ENABLED is '0') or when the RX FIFO is empty, a read from
this register returns 0xffff:ffff. This register should only be used in FIFO mode (and not in EZ or
CMD_RESP modes). This register is 'read only'; a write to this register is ignored.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name DATA [7:0]
Bits 15 14 13 12 11 10 9 8
Name DATA [15:8]
Bits 23 22 21 20 19 18 17 16
Name DATA [23:16]
Bits 31 30 29 28 27 26 25 24
Name DATA [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 DATA R W Undefined Data read from the receiver FIFO. Reading a data
frame will remove the data frame from the FIFO; i.e.
behavior is similar to that of a POP operation. Note
that when CTRL.MEM_WIDTH is '0', only DATA[7:0]
are used and when CTRL.MEM_WIDTH is '1', only
DATA[15:0] are used
A read from an empty RX FIFO sets
INTR_RX.UNDERFLOW to '1'.
When this register is read through the debugger, the
data frame will not be removed from the FIFO. Similar
in operation to RX_FIFO_RD_SILENT
1425
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers