Infineon TRAVEO T2G - 26.8.3 CLK_DSI_SELECT

Technical Reference Manual 002-29852 Rev. *B
26.8.3 CLK_DSI_SELECT
Description:
Clock DSI Select Register
Address:
0x40260100
Offset:
0x100
Retention:
Retained
IsDeepSleep:
Yes
Comment:
Configures DSI mux in clock generation path. Each path has its own copy of this register. See
PAS for DSI signal connectivity list.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:5] DSI_MUX [4:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:4 DSI_MUX RW R 0 Selects a DSI source or low frequency clock for use in
a clock path. The output of this mux can be selected
for clock PATH<i> using CLK_PATH_SELECT
register. Using the output of this mux as HFCLK
source will result in undefined behavior. It can be used
to clocks to DSI or as reference inputs for the FLL/PLL,
subject to the frequency limits of those circuits. This
mux is not glitch free, so do not change the selection
while it is an actively selected clock.
DSI_OUT0 0 DSI0 - dsi_out[0]
DSI_OUT1 1 DSI1 - dsi_out[1]
DSI_OUT2 2 DSI2 - dsi_out[2]
DSI_OUT3 3 DSI3 - dsi_out[3]
DSI_OUT4 4 DSI4 - dsi_out[4]
DSI_OUT5 5 DSI5 - dsi_out[5]
DSI_OUT6 6 DSI6 - dsi_out[6]
DSI_OUT7 7 DSI7 - dsi_out[7]
DSI_OUT8 8 DSI8 - dsi_out[8]
DSI_OUT9 9 DSI9 - dsi_out[9]
DSI_OUT10 10 DSI10 - dsi_out[10]
DSI_OUT11 11 DSI11 - dsi_out[11]
DSI_OUT12 12 DSI12 - dsi_out[12]
DSI_OUT13 13 DSI13 - dsi_out[13]
DSI_OUT14 14 DSI14 - dsi_out[14]
DSI_OUT15 15 DSI15 - dsi_out[15]
ILO0 16 ILO0 - Internal Low-speed Oscillator #0
WCO 17 WCO - Watch-Crystal Oscillator
ALTLF 18 ALTLF - Alternate Low-Frequency Clock
PILO 19 PILO - Precision Internal Low-speed Oscillator
ILO1 20 ILO1 - Internal Low-speed Oscillator #1, if present.
1631
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers