Infineon TRAVEO T2G - 5.1.4 CPUSS_CM4_CTL

Technical Reference Manual 002-29852 Rev. *B
5.1.4 CPUSS_CM4_CTL
Description:
CM4 control
Address:
0x4020000C
Offset:
0xC
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name IDC_MASK
[31:31]
None [30:29] IXC_MASK
[28:28]
UFC_MASK
[27:27]
OFC
_MASK
[26:26]
DZC_MASK
[25:25]
IOC_MASK
[24:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
24 IOC_MASK RW R 0 CPU floating point unit (FPU) exception mask for the
CPU's FPCSR.IOC 'invalid operation' exception
condition:
'0': The CPU's exception condition does NOT activate
the CPU's floating point interrupt.
'1': the CPU's exception condition activates the CPU's
floating point interrupt.
Note: the ARM architecture does NOT support FPU
exceptions; i.e. there is no precise FPU exception
handler. Instead, FPU conditions are captured in the
CPU's FPCSR register and the conditions are provided
as CPU interface signals. The interface signals are
'masked' with the fields a provide by this register
(CM7_0_CTL). The 'masked' signals are reduced/OR-
ed into a single CPU floating point interrupt signal. The
associated CPU interrupt handler allows for imprecise
handling of FPU exception conditions.
Note: the CPU's FPCSR exception conditions are
'sticky'. Typically, the CPU FPU interrupt handler will
clear the exception condition(s) to '0'.
Note: by default, the FPU exception masks are '0'.
Therefore, FPU exception conditions will NOT activate
the CPU's floating point interrupt.
25 DZC_MASK RW R 0 CPU FPU exception mask for the CPU's FPCSR.DZC
'divide by zero' exception condition:
'0': The CPU's exception condition does NOT activate
the CPU's floating point interrupt.
'1': the CPU's exception condition activates the CPU's
floating point interrupt.
705
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers