Technical Reference Manual 002-29852 Rev. *B
9.2.1.31 CH_STRUCT 30
Register Name Address Permission Description
DW1_CH_STRUCT30_CH_CTL
0x40298780 FULL Channel control
DW1_CH_STRUCT30_CH_STATUS
0x40298784 FULL Channel status
DW1_CH_STRUCT30_CH_IDX
0x40298788 FULL Channel current indices
DW1_CH_STRUCT30_CH_CURR_PTR
0x4029878C FULL Channel current descriptor pointer
DW1_CH_STRUCT30_INTR
0x40298790 FULL Interrupt
DW1_CH_STRUCT30_INTR_SET
0x40298794 FULL Interrupt set
DW1_CH_STRUCT30_INTR_MASK
0x40298798 FULL Interrupt mask
DW1_CH_STRUCT30_INTR_MASKED
0x4029879C FULL Interrupt masked
DW1_CH_STRUCT30_SRAM_DATA0
0x402987A0 FULL SRAM data 0
DW1_CH_STRUCT30_SRAM_DATA1
0x402987A4 FULL SRAM data 1
DW1_CH_STRUCT30_TR_CMD
0x402987A8 FULL Channel software trigger
9.2.1.32 CH_STRUCT 31
Register Name Address Permission Description
DW1_CH_STRUCT31_CH_CTL
0x402987C0 FULL Channel control
DW1_CH_STRUCT31_CH_STATUS
0x402987C4 FULL Channel status
DW1_CH_STRUCT31_CH_IDX
0x402987C8 FULL Channel current indices
DW1_CH_STRUCT31_CH_CURR_PTR
0x402987CC FULL Channel current descriptor pointer
DW1_CH_STRUCT31_INTR
0x402987D0 FULL Interrupt
DW1_CH_STRUCT31_INTR_SET
0x402987D4 FULL Interrupt set
DW1_CH_STRUCT31_INTR_MASK
0x402987D8 FULL Interrupt mask
DW1_CH_STRUCT31_INTR_MASKED
0x402987DC FULL Interrupt masked
DW1_CH_STRUCT31_SRAM_DATA0
0x402987E0 FULL SRAM data 0
DW1_CH_STRUCT31_SRAM_DATA1
0x402987E4 FULL SRAM data 1
DW1_CH_STRUCT31_TR_CMD
0x402987E8 FULL Channel software trigger
9.2.1.33 CH_STRUCT 32
Register Name Address Permission Description
DW1_CH_STRUCT32_CH_CTL
0x40298800 FULL Channel control
DW1_CH_STRUCT32_CH_STATUS
0x40298804 FULL Channel status
DW1_CH_STRUCT32_CH_IDX
0x40298808 FULL Channel current indices
DW1_CH_STRUCT32_CH_CURR_PTR
0x4029880C FULL Channel current descriptor pointer
DW1_CH_STRUCT32_INTR
0x40298810 FULL Interrupt
DW1_CH_STRUCT32_INTR_SET
0x40298814 FULL Interrupt set
DW1_CH_STRUCT32_INTR_MASK
0x40298818 FULL Interrupt mask
DW1_CH_STRUCT32_INTR_MASKED
0x4029881C FULL Interrupt masked
DW1_CH_STRUCT32_SRAM_DATA0
0x40298820 FULL SRAM data 0
DW1_CH_STRUCT32_SRAM_DATA1
0x40298824 FULL SRAM data 1
DW1_CH_STRUCT32_TR_CMD
0x40298828 FULL Channel software trigger
9.2.1.34 CH_STRUCT 33
Register Name Address Permission Description
DW1_CH_STRUCT33_CH_CTL
0x40298840 FULL Channel control
DW1_CH_STRUCT33_CH_STATUS
0x40298844 FULL Channel status
DW1_CH_STRUCT33_CH_IDX
0x40298848 FULL Channel current indices
DW1_CH_STRUCT33_CH_CURR_PTR
0x4029884C FULL Channel current descriptor pointer
DW1_CH_STRUCT33_INTR
0x40298850 FULL Interrupt
DW1_CH_STRUCT33_INTR_SET
0x40298854 FULL Interrupt set
DW1_CH_STRUCT33_INTR_MASK
0x40298858 FULL Interrupt mask
DW1_CH_STRUCT33_INTR_MASKED
0x4029885C FULL Interrupt masked
DW1_CH_STRUCT33_SRAM_DATA0
0x40298860 FULL SRAM data 0
DW1_CH_STRUCT33_SRAM_DATA1
0x40298864 FULL SRAM data 1
DW1_CH_STRUCT33_TR_CMD
0x40298868 FULL Channel software trigger
9.2.1.35 CH_STRUCT 34
Register Name Address Permission Description
DW1_CH_STRUCT34_CH_CTL
0x40298880 FULL Channel control
DW1_CH_STRUCT34_CH_STATUS
0x40298884 FULL Channel status
DW1_CH_STRUCT34_CH_IDX
0x40298888 FULL Channel current indices
DW1_CH_STRUCT34_CH_CURR_PTR
0x4029888C FULL Channel current descriptor pointer
DW1_CH_STRUCT34_INTR
0x40298890 FULL Interrupt
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers