Technical Reference Manual 002-29852 Rev. *B
26.8.48 CSV_LF
26.8.48.1 CSV
26.8.48.1.1 CSV_LF_CSV_REF_CTL
Description:
Clock Supervision Reference Control
Address:
0x40261720
Offset:
0x0
Retention:
Retained
IsDeepSleep:
No
Comment:
Controls clock supervision for a clock tree.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name STARTUP [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name CSV_EN
[31:31]
None [30:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 STARTUP RW R 0 Startup delay time -1 (in reference clock cycles), after
enable, from reference clock start to monitored clock
start.
At a minimum (both clocks running): STARTUP >=
(PERIOD +3) * FREQ_RATIO - UPPER, with
FREQ_RATIO = (Reference frequency / Monitored
frequency)
On top of that the actual clock startup delay and the
margin for accuracy of both clocks must be added.
31 CSV_EN RW R 0 Enables clock supervision, both frequency and loss.
CSV in Active domain: Clock supervision is reset
during DeepSleep and Hibernate modes. When
enabled it begins operating automatically after a
DeepSleep wakeup, but it must be reconfigured after
Hibernate wakeup.
CSV in DeepSleep domain: Clock supervision is reset
during Hibernate mode. It must be reconfigured after
Hibernate wakeup.
CSV in Backup domain: Clock supervision operates
during Hibernate mode, can be configured to wake
from Hibernate, and continues operating during reboot.
A CSV error detection is reported to the Fault
structure.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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