Infineon TRAVEO T2G - 20.30.10 TR_GR; 20.30.10.1 PERI_TR_GR_TR_CTL

Technical Reference Manual 002-29852 Rev. *B
20.30.10 TR_GR
20.30.10.1 PERI_TR_GR_TR_CTL
Description:
Trigger control register
Address:
0x40008000
Offset:
0x0
Retention:
Retained
IsDeepSleep:
No
Comment:
This register specifies the input trigger for a specific output trigger in trigger group 0. Note that
for SW initiated triggers, SW is responsible for activating the output trigger, rather than relying
on a specific HW input trigger. For this reason, input trigger 0 is typically connected to a
constant signal level of '0' at chip integration (design decision) and SW initiated output triggers
are all connected to input trigger 0 (SW responsibility: TR_OUT_CTL.TR_SEL should be set to
'0' to select the constant signal level '0' from chip level). As a result, SW initiated triggers can
never be activated by a HW input trigger to the trigger multiplexer.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name TR_SEL [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:13] DBG
_FREEZE
_EN [12:12]
None [11:10] TR_EDGE
[9:9]
TR_INV
[8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 TR_SEL RW R 0 Specifies input trigger. This field is typically set during
the setup of a chip use case scenario. Changing this
field while activated triggers are present on the input
triggers may result in unpredictable behavior. Note that
input trigger 0 (default value) is typically connected to
a constant signal level of '0', and as a result will not
cause HW activation of the output trigger.
8 TR_INV RW R 0 Specifies if the output trigger is inverted.
9 TR_EDGE RW R 0 Specifies if the (inverted) output trigger is treated as a
level sensitive or edge sensitive trigger.
'0': level sensitive.
'1': edge sensitive trigger. The (inverted) output trigger
duration needs to be at least 2 cycles on the consumer
clock. the(inverted) output trigger is synchronized to
the consumer clock and a two cycle pulse is generated
on the consumer clock.
12 DBG_FREEZE_EN RW R 0 Specifies if the output trigger is blocked in debug
mode. When set high tr_dbg_freeze will block the
output trigger generation.
1153
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers