Infineon TRAVEO T2G - 4.13.2.13 CM4_DWT_MASK1

Technical Reference Manual 002-29852 Rev. *B
4.13.2.13 CM4_DWT_MASK1
Description:
Comparator Mask registers
Address:
0xE0001034
Offset:
0x34
Retention:
Retained
IsDeepSleep:
No
Comment:
The MASKn register characteristics are:
Purpose: Provides the size of the ignore mask applied to the access address for address
range matching by comparator n.
Usage constraints: The operation of comparator n depends also on the registers COMPn and
FUNCTIONn, see Comparator registers, COMPn and Comparator Function registers,
FUNCTIONn on Arm TRM page C1-806.
Configurations:
Implemented only when CTRL.NUMCOMP is nonzero, see Control register, CTRL on Arm
TRM page C1-797.
CTRL.NUMCOMP defines the number of implemented MASKn registers. Implemented
MASKn registers number from 0 to (NUMCOMP-1). Unimplemented registers are UNK/SBZP.
Attributes: See Table C1-21 on Arm TRM page C1-797.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:5] MASK [4:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:4 MASK RW R 0 The size of the ignore mask, 0-31 bits, applied to
address range matching.
The maximum mask size is IMPLEMENTATION
DEFINED. A debugger can write 0b11111 to this field
and then read the register back to determine the
maximum mask size supported.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers