Technical Reference Manual 002-29852 Rev. *B
Register Name Address Permission Description
DW0_CH_STRUCT29_CH_CURR_PTR
0x4028874C FULL Channel current descriptor pointer
DW0_CH_STRUCT29_INTR
0x40288750 FULL Interrupt
DW0_CH_STRUCT29_INTR_SET
0x40288754 FULL Interrupt set
DW0_CH_STRUCT29_INTR_MASK
0x40288758 FULL Interrupt mask
DW0_CH_STRUCT29_INTR_MASKED
0x4028875C FULL Interrupt masked
DW0_CH_STRUCT29_SRAM_DATA0
0x40288760 FULL SRAM data 0
DW0_CH_STRUCT29_SRAM_DATA1
0x40288764 FULL SRAM data 1
DW0_CH_STRUCT29_TR_CMD
0x40288768 FULL Channel software trigger
9.1.1.31 CH_STRUCT 30
Register Name Address Permission Description
DW0_CH_STRUCT30_CH_CTL
0x40288780 FULL Channel control
DW0_CH_STRUCT30_CH_STATUS
0x40288784 FULL Channel status
DW0_CH_STRUCT30_CH_IDX
0x40288788 FULL Channel current indices
DW0_CH_STRUCT30_CH_CURR_PTR
0x4028878C FULL Channel current descriptor pointer
DW0_CH_STRUCT30_INTR
0x40288790 FULL Interrupt
DW0_CH_STRUCT30_INTR_SET
0x40288794 FULL Interrupt set
DW0_CH_STRUCT30_INTR_MASK
0x40288798 FULL Interrupt mask
DW0_CH_STRUCT30_INTR_MASKED
0x4028879C FULL Interrupt masked
DW0_CH_STRUCT30_SRAM_DATA0
0x402887A0 FULL SRAM data 0
DW0_CH_STRUCT30_SRAM_DATA1
0x402887A4 FULL SRAM data 1
DW0_CH_STRUCT30_TR_CMD
0x402887A8 FULL Channel software trigger
9.1.1.32 CH_STRUCT 31
Register Name Address Permission Description
DW0_CH_STRUCT31_CH_CTL
0x402887C0 FULL Channel control
DW0_CH_STRUCT31_CH_STATUS
0x402887C4 FULL Channel status
DW0_CH_STRUCT31_CH_IDX
0x402887C8 FULL Channel current indices
DW0_CH_STRUCT31_CH_CURR_PTR
0x402887CC FULL Channel current descriptor pointer
DW0_CH_STRUCT31_INTR
0x402887D0 FULL Interrupt
DW0_CH_STRUCT31_INTR_SET
0x402887D4 FULL Interrupt set
DW0_CH_STRUCT31_INTR_MASK
0x402887D8 FULL Interrupt mask
DW0_CH_STRUCT31_INTR_MASKED
0x402887DC FULL Interrupt masked
DW0_CH_STRUCT31_SRAM_DATA0
0x402887E0 FULL SRAM data 0
DW0_CH_STRUCT31_SRAM_DATA1
0x402887E4 FULL SRAM data 1
DW0_CH_STRUCT31_TR_CMD
0x402887E8 FULL Channel software trigger
9.1.1.33 CH_STRUCT 32
Register Name Address Permission Description
DW0_CH_STRUCT32_CH_CTL
0x40288800 FULL Channel control
DW0_CH_STRUCT32_CH_STATUS
0x40288804 FULL Channel status
DW0_CH_STRUCT32_CH_IDX
0x40288808 FULL Channel current indices
DW0_CH_STRUCT32_CH_CURR_PTR
0x4028880C FULL Channel current descriptor pointer
DW0_CH_STRUCT32_INTR
0x40288810 FULL Interrupt
DW0_CH_STRUCT32_INTR_SET
0x40288814 FULL Interrupt set
DW0_CH_STRUCT32_INTR_MASK
0x40288818 FULL Interrupt mask
DW0_CH_STRUCT32_INTR_MASKED
0x4028881C FULL Interrupt masked
DW0_CH_STRUCT32_SRAM_DATA0
0x40288820 FULL SRAM data 0
DW0_CH_STRUCT32_SRAM_DATA1
0x40288824 FULL SRAM data 1
DW0_CH_STRUCT32_TR_CMD
0x40288828 FULL Channel software trigger
9.1.1.34 CH_STRUCT 33
Register Name Address Permission Description
DW0_CH_STRUCT33_CH_CTL
0x40288840 FULL Channel control
DW0_CH_STRUCT33_CH_STATUS
0x40288844 FULL Channel status
DW0_CH_STRUCT33_CH_IDX
0x40288848 FULL Channel current indices
DW0_CH_STRUCT33_CH_CURR_PTR
0x4028884C FULL Channel current descriptor pointer
DW0_CH_STRUCT33_INTR
0x40288850 FULL Interrupt
DW0_CH_STRUCT33_INTR_SET
0x40288854 FULL Interrupt set
DW0_CH_STRUCT33_INTR_MASK
0x40288858 FULL Interrupt mask
DW0_CH_STRUCT33_INTR_MASKED
0x4028885C FULL Interrupt masked
DW0_CH_STRUCT33_SRAM_DATA0
0x40288860 FULL SRAM data 0
DW0_CH_STRUCT33_SRAM_DATA1
0x40288864 FULL SRAM data 1
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers