Infineon TRAVEO T2G - 9.2.1.13 CH_STRUCT 12; 9.2.1.14 CH_STRUCT 13; 9.2.1.15 CH_STRUCT 14; 9.2.1.16 CH_STRUCT 15

Technical Reference Manual 002-29852 Rev. *B
9.2.1.13 CH_STRUCT 12
Register Name Address Permission Description
DW1_CH_STRUCT12_CH_CTL
0x40298300 FULL Channel control
DW1_CH_STRUCT12_CH_STATUS
0x40298304 FULL Channel status
DW1_CH_STRUCT12_CH_IDX
0x40298308 FULL Channel current indices
DW1_CH_STRUCT12_CH_CURR_PTR
0x4029830C FULL Channel current descriptor pointer
DW1_CH_STRUCT12_INTR
0x40298310 FULL Interrupt
DW1_CH_STRUCT12_INTR_SET
0x40298314 FULL Interrupt set
DW1_CH_STRUCT12_INTR_MASK
0x40298318 FULL Interrupt mask
DW1_CH_STRUCT12_INTR_MASKED
0x4029831C FULL Interrupt masked
DW1_CH_STRUCT12_SRAM_DATA0
0x40298320 FULL SRAM data 0
DW1_CH_STRUCT12_SRAM_DATA1
0x40298324 FULL SRAM data 1
DW1_CH_STRUCT12_TR_CMD
0x40298328 FULL Channel software trigger
9.2.1.14 CH_STRUCT 13
Register Name Address Permission Description
DW1_CH_STRUCT13_CH_CTL
0x40298340 FULL Channel control
DW1_CH_STRUCT13_CH_STATUS
0x40298344 FULL Channel status
DW1_CH_STRUCT13_CH_IDX
0x40298348 FULL Channel current indices
DW1_CH_STRUCT13_CH_CURR_PTR
0x4029834C FULL Channel current descriptor pointer
DW1_CH_STRUCT13_INTR
0x40298350 FULL Interrupt
DW1_CH_STRUCT13_INTR_SET
0x40298354 FULL Interrupt set
DW1_CH_STRUCT13_INTR_MASK
0x40298358 FULL Interrupt mask
DW1_CH_STRUCT13_INTR_MASKED
0x4029835C FULL Interrupt masked
DW1_CH_STRUCT13_SRAM_DATA0
0x40298360 FULL SRAM data 0
DW1_CH_STRUCT13_SRAM_DATA1
0x40298364 FULL SRAM data 1
DW1_CH_STRUCT13_TR_CMD
0x40298368 FULL Channel software trigger
9.2.1.15 CH_STRUCT 14
Register Name Address Permission Description
DW1_CH_STRUCT14_CH_CTL
0x40298380 FULL Channel control
DW1_CH_STRUCT14_CH_STATUS
0x40298384 FULL Channel status
DW1_CH_STRUCT14_CH_IDX
0x40298388 FULL Channel current indices
DW1_CH_STRUCT14_CH_CURR_PTR
0x4029838C FULL Channel current descriptor pointer
DW1_CH_STRUCT14_INTR
0x40298390 FULL Interrupt
DW1_CH_STRUCT14_INTR_SET
0x40298394 FULL Interrupt set
DW1_CH_STRUCT14_INTR_MASK
0x40298398 FULL Interrupt mask
DW1_CH_STRUCT14_INTR_MASKED
0x4029839C FULL Interrupt masked
DW1_CH_STRUCT14_SRAM_DATA0
0x402983A0 FULL SRAM data 0
DW1_CH_STRUCT14_SRAM_DATA1
0x402983A4 FULL SRAM data 1
DW1_CH_STRUCT14_TR_CMD
0x402983A8 FULL Channel software trigger
9.2.1.16 CH_STRUCT 15
Register Name Address Permission Description
DW1_CH_STRUCT15_CH_CTL
0x402983C0 FULL Channel control
DW1_CH_STRUCT15_CH_STATUS
0x402983C4 FULL Channel status
DW1_CH_STRUCT15_CH_IDX
0x402983C8 FULL Channel current indices
DW1_CH_STRUCT15_CH_CURR_PTR
0x402983CC FULL Channel current descriptor pointer
DW1_CH_STRUCT15_INTR
0x402983D0 FULL Interrupt
DW1_CH_STRUCT15_INTR_SET
0x402983D4 FULL Interrupt set
DW1_CH_STRUCT15_INTR_MASK
0x402983D8 FULL Interrupt mask
DW1_CH_STRUCT15_INTR_MASKED
0x402983DC FULL Interrupt masked
DW1_CH_STRUCT15_SRAM_DATA0
0x402983E0 FULL SRAM data 0
DW1_CH_STRUCT15_SRAM_DATA1
0x402983E4 FULL SRAM data 1
DW1_CH_STRUCT15_TR_CMD
0x402983E8 FULL Channel software trigger
9.2.1.17 CH_STRUCT 16
Register Name Address Permission Description
DW1_CH_STRUCT16_CH_CTL
0x40298400 FULL Channel control
DW1_CH_STRUCT16_CH_STATUS
0x40298404 FULL Channel status
DW1_CH_STRUCT16_CH_IDX
0x40298408 FULL Channel current indices
DW1_CH_STRUCT16_CH_CURR_PTR
0x4029840C FULL Channel current descriptor pointer
DW1_CH_STRUCT16_INTR
0x40298410 FULL Interrupt
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