Technical Reference Manual 002-29852 Rev. *B
5.1.28 CPUSS_CM4_PWR_CTL
Description:
CM4 power control
Address:
0x40201200
Offset:
0x1200
Retention:
Retained
IsDeepSleep:
No
Comment:
This register controls the CM4 power state. Please note that this register must not be modified
while the CM4 is executing; doing so may corrupt/abort pending bus transaction by the CM4
and cause unexpected behaviors in the system, including deadlock. The intended usage of
this register is by the CM0+ while the CM4 is in DeepSleep mode.
Default:
0xFA050001
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:2] PWR_MODE [1:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name VECTKEYSTAT [23:16]
Bits 31 30 29 28 27 26 25 24
Name VECTKEYSTAT [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:1 PWR_MODE RW R 1 Power mode.
OFF 0 Switch CM4 off
Power off, clock off, isolate, reset and no retain.
RESET 1 Reset CM4
Clock off, no isolated, no retain and reset.
Note: The CM4 CPU has a AIRCR.SYSRESETREQ
register field that allows the CM4 to reset the complete
device (RESET only resets the CM4), resulting in a
warm boot.
RETAINED 2 Put CM4 in Retained mode
This can only become effective if CM4 is in SleepDeep
mode. Check PWR_DONE flag to see if CM4
RETAINED state has been reached.
Power off, clock off, isolate, no reset and retain.
ENABLED 3 Switch CM4 on.
Power on, clock on, no isolate, no reset and no retain.
16:31 VECTKEYSTAT R 64005 Register key (to prevent accidental writes).
- Should be written with a 0x05fa key value for the
write to take effect.
- Always reads as 0xfa05.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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