Technical Reference Manual 002-29852 Rev. *B
20.30.9.2 PERI_GR_SL_CTL
Description:
Slave control
Address:
0x40004010
Offset:
0x10
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0xFFFF
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name ENABLED
_7 [7:7]
ENABLED
_6 [6:6]
ENABLED
_5 [5:5]
ENABLED
_4 [4:4]
ENABLED
_3 [3:3]
ENABLED
_2 [2:2]
ENABLED
_1 [1:1]
ENABLED
_0 [0:0]
Bits 15 14 13 12 11 10 9 8
Name ENABLED
_15 [15:15]
ENABLED
_14 [14:14]
ENABLED
_13 [13:13]
ENABLED
_12 [12:12]
ENABLED
_11 [11:11]
ENABLED
_10 [10:10]
ENABLED
_9 [9:9]
ENABLED
_8 [8:8]
Bits 23 22 21 20 19 18 17 16
Name DISABLED
_7 [23:23]
DISABLED
_6 [22:22]
DISABLED
_5 [21:21]
DISABLED
_4 [20:20]
DISABLED
_3 [19:19]
DISABLED
_2 [18:18]
DISABLED
_1 [17:17]
DISABLED
_0 [16:16]
Bits 31 30 29 28 27 26 25 24
Name DISABLED
_15 [31:31]
DISABLED
_14 [30:30]
DISABLED
_13 [29:29]
DISABLED
_12 [28:28]
DISABLED
_11 [27:27]
DISABLED
_10 [26:26]
DISABLED
_9 [25:25]
DISABLED
_8 [24:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 ENABLED_0 RW R 1 Peripheral group, slave 0 enable. If the slave is
disabled, its clock is gated off (constant '0') and its
resets are activated.
Note: For peripheral group 0 (the peripheral
interconnect MMIO registers), this field is a constant '1'
(SW: R): the slave can NOT be disabled.
1 ENABLED_1 RW R 1 Peripheral group, slave 1 enable. If the slave is
disabled, its clock is gated off (constant '0') and its
resets are activated.
Note: For peripheral group 0 (the peripheral
interconnect, master interface MMIO registers), this
field is a constant '1' (SW: R): the slave can NOT be
disabled.
2 ENABLED_2 RW R 1 N/A
3 ENABLED_3 RW R 1 N/A
4 ENABLED_4 RW R 1 N/A
5 ENABLED_5 RW R 1 N/A
6 ENABLED_6 RW R 1 N/A
7 ENABLED_7 RW R 1 N/A
8 ENABLED_8 RW R 1 N/A
9 ENABLED_9 RW R 1 N/A
10 ENABLED_10 RW R 1 N/A
11 ENABLED_11 RW R 1 N/A
12 ENABLED_12 RW R 1 N/A
13 ENABLED_13 RW R 1 N/A
14 ENABLED_14 RW R 1 N/A
15 ENABLED_15 RW R 1 N/A
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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