Technical Reference Manual 002-29852 Rev. *B
Register Name Address Permission Description
TCPWM0_GRP1_CNT11_INTR
0x403885F0 FULL Interrupt request register
TCPWM0_GRP1_CNT11_INTR_SET
0x403885F4 FULL Interrupt set request register
TCPWM0_GRP1_CNT11_INTR_MASK
0x403885F8 FULL Interrupt mask register
TCPWM0_GRP1_CNT11_INTR_MASKED
0x403885FC FULL Interrupt masked request register
28.3 GRP 2
28.3.1 CNT 0
Register Name Address Permission Description
TCPWM0_GRP2_CNT0_CTRL
0x40390000 FULL Counter control register
Note:AUTO_RELOAD_LINE_SEL CC0_MATCH_UP_EN
CC0_MATCH_DOWN_EN CC1_MATCH_UP_EN
CC1_MATCH_DOWN_EN are not available for this
register
TCPWM0_GRP2_CNT0_STATUS
0x40390004 FULL Counter status register
Note:DT_CNT_H is not available for this register
TCPWM0_GRP2_CNT0_COUNTER
0x40390008 FULL Counter count register
TCPWM0_GRP2_CNT0_CC0
0x40390010 FULL Counter compare/capture 0 register
TCPWM0_GRP2_CNT0_CC0_BUFF
0x40390014 FULL Counter buffered compare/capture 0 register
TCPWM0_GRP2_CNT0_CC1
0x40390018 FULL Counter compare/capture 1 register
TCPWM0_GRP2_CNT0_CC1_BUFF
0x4039001C FULL Counter buffered compare/capture 1 register
TCPWM0_GRP2_CNT0_PERIOD
0x40390020 FULL Counter period register
TCPWM0_GRP2_CNT0_PERIOD_BUFF
0x40390024 FULL Counter buffered period register
TCPWM0_GRP2_CNT0_DT
0x40390030 FULL Counter PWM dead time register
Note:DT_LINE_OUT_H DT_LINE_COMPL_OUT are not
available for this register
TCPWM0_GRP2_CNT0_TR_CMD
0x40390040 FULL Counter trigger command register
TCPWM0_GRP2_CNT0_TR_IN_SEL0
0x40390044 FULL Counter input trigger selection register 0
TCPWM0_GRP2_CNT0_TR_IN_SEL1
0x40390048 FULL Counter input trigger selection register 1
TCPWM0_GRP2_CNT0_TR_IN_EDGE_SEL
0x4039004C FULL Counter input trigger edge selection register
TCPWM0_GRP2_CNT0_TR_PWM_CTRL
0x40390050 FULL Counter trigger PWM control register
TCPWM0_GRP2_CNT0_TR_OUT_SEL
0x40390054 FULL Counter output trigger selection register
TCPWM0_GRP2_CNT0_INTR
0x40390070 FULL Interrupt request register
TCPWM0_GRP2_CNT0_INTR_SET
0x40390074 FULL Interrupt set request register
TCPWM0_GRP2_CNT0_INTR_MASK
0x40390078 FULL Interrupt mask register
TCPWM0_GRP2_CNT0_INTR_MASKED
0x4039007C FULL Interrupt masked request register
28.3.2 CNT 1
Register Name Address Permission Description
TCPWM0_GRP2_CNT1_CTRL
0x40390080 FULL Counter control register
Note:AUTO_RELOAD_LINE_SEL CC0_MATCH_UP_EN
CC0_MATCH_DOWN_EN CC1_MATCH_UP_EN
CC1_MATCH_DOWN_EN are not available for this
register
TCPWM0_GRP2_CNT1_STATUS
0x40390084 FULL Counter status register
Note:DT_CNT_H is not available for this register
TCPWM0_GRP2_CNT1_COUNTER
0x40390088 FULL Counter count register
TCPWM0_GRP2_CNT1_CC0
0x40390090 FULL Counter compare/capture 0 register
TCPWM0_GRP2_CNT1_CC0_BUFF
0x40390094 FULL Counter buffered compare/capture 0 register
TCPWM0_GRP2_CNT1_CC1
0x40390098 FULL Counter compare/capture 1 register
TCPWM0_GRP2_CNT1_CC1_BUFF
0x4039009C FULL Counter buffered compare/capture 1 register
TCPWM0_GRP2_CNT1_PERIOD
0x403900A0 FULL Counter period register
TCPWM0_GRP2_CNT1_PERIOD_BUFF
0x403900A4 FULL Counter buffered period register
TCPWM0_GRP2_CNT1_DT
0x403900B0 FULL Counter PWM dead time register
Note:DT_LINE_OUT_H DT_LINE_COMPL_OUT are not
available for this register
TCPWM0_GRP2_CNT1_TR_CMD
0x403900C0 FULL Counter trigger command register
TCPWM0_GRP2_CNT1_TR_IN_SEL0
0x403900C4 FULL Counter input trigger selection register 0
TCPWM0_GRP2_CNT1_TR_IN_SEL1
0x403900C8 FULL Counter input trigger selection register 1
TCPWM0_GRP2_CNT1_TR_IN_EDGE_SEL
0x403900CC FULL Counter input trigger edge selection register
TCPWM0_GRP2_CNT1_TR_PWM_CTRL
0x403900D0 FULL Counter trigger PWM control register
TCPWM0_GRP2_CNT1_TR_OUT_SEL
0x403900D4 FULL Counter output trigger selection register
TCPWM0_GRP2_CNT1_INTR
0x403900F0 FULL Interrupt request register
TCPWM0_GRP2_CNT1_INTR_SET
0x403900F4 FULL Interrupt set request register
TCPWM0_GRP2_CNT1_INTR_MASK
0x403900F8 FULL Interrupt mask register
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers