Infineon TRAVEO T2G - 3.8.2.5 CM0 P_BP_BP_COMP3

Technical Reference Manual 002-29852 Rev. *B
3.8.2.5 CM0P_BP_BP_COMP3
Description:
Breakpoint Compare Register
Address:
0xE0002014
Offset:
0x14
Retention:
Retained
IsDeepSleep:
No
Comment:
Holds a breakpoint address for comparison with instruction addresses in the Code
memory region, see The system address map on Arm TRM page B3-258 for more information.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [1:1] ENABLE
[0:0]
Bits 15 14 13 12 11 10 9 8
Name COMP_ADDR [15:8]
Bits 23 22 21 20 19 18 17 16
Name COMP_ADDR [23:16]
Bits 31 30 29 28 27 26 25 24
Name MATCH [31:30] None
[29:29]
COMP_ADDR [28:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 ENABLE RW R 0 Enables the comparator.
Note BP_CTRL.ENABLE must also be set to 1 to
enable a comparator.
2:28 COMP_ADDR RW R X Stores bits [28:2] of the comparison address. The
comparison address is compared with the address
from the Code memory region. Bits [31:29] and [1:0] of
the comparison address are zero.
30:31 MATCH RW R X BP_MATCH defines the behavior when the COMP
address is matched.
NONE 0 No breakpoint matching
LOWER 1 Breakpoint on lower halfword, upper is unaffected.
UPPER 2 Breakpoint on upper halfword, lower is unaffected.
BOTH 3 Breakpoint on both lower and upper halfwords.
152
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers