Technical Reference Manual 002-29852 Rev. *B
23.9.4 SCB_CMD_RESP_STATUS
Description:
Command/response status
Address:
0x4060000C
Offset:
0xC
Retention:
Not Retained
IsDeepSleep:
No
Comment:
The register fields reflect register states without a default/reset value (CURR_RD_ADDR and
CURR_WR_ADDR) or reflect an external bus state. Therefore, these registers are undefined
after the IP is enabled.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name CURR_RD_ADDR [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:9] CURR_RD
_ADDR
[8:8]
Bits 23 22 21 20 19 18 17 16
Name CURR_WR_ADDR [23:16]
Bits 31 30 29 28 27 26 25 24
Name CMD
_RESP_EC
_BUSY
[31:31]
CMD
_RESP_EC
_BUS_BUS
Y [30:30]
None [29:25] CURR_WR
_ADDR
[24:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:8 CURR_RD_ADDR R W Undefined I2C/SPI read current address for CMD_RESP mode.
HW increments the field after a read access to the
memory buffer. However, when the last memory buffer
address is reached, the address is NOT incremented
(but remains at the maximum memory buffer address).
The field is used to determine how many bytes have
been read (# bytes = CURR_RD_ADDR -
CMD_RESP_CTRL.BASE_RD_ADDR).
This field is reliable when there is no bus transfer. This
field is potentially unreliable when there is a ongoing
bus transfer, i.e. when CMD_RESP_EC_BUSY is '0',
the field is reliable.
16:24 CURR_WR_ADDR R W Undefined I2C/SPI write current address for CMD_RESP mode.
HW increments the field after a write access to the
memory buffer. However, when the last memory buffer
address is reached, the address is NOT incremented
(but remains at the maximum memory buffer address).
The field is used to determine how many bytes have
been written (# bytes = CURR_WR_ADDR -
CMD_RESP_CTRL.BASE_WR_ADDR).
This field is reliable when there is no bus transfer. This
field is potentially unreliable when there is a ongoing
bus transfer, i.e. when CMD_RESP_EC_BUSY is '0',
the field is reliable.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers