Infineon TRAVEO T2G - Page 1390

Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
30 CMD_RESP_EC_BUS
_BUSY
R W Undefined Indicates whether there is an ongoing bus transfer to
the IP.
'0': no ongoing bus transfer.
'1': ongoing bus transfer.
For SPI, the field is '1' when slave mode is selected.
For I2C, the field is set to '1' at a I2C
START/RESTART. In case of an address match, the
field is set to '0' on a I2C STOP. In case of NO address
match, the field is set to '0' after the failing address
match.
31 CMD_RESP_EC_BUSY R W Undefined Indicates whether the CURR_RD_ADDR and
CURR_WR_ADDR fields in this register are reliable
(when CMD_RESP_EC_BUSY is '0') or not reliable
(when CMD_RESP_EC_BUSY is '1'). Note:
- When there is no ongoing bus transfer,
CMD_RESP_EC_BUSY is '0' (reliable).
- When there is a ongoing bus transfer,
CMD_RESP_EC_BUSY is '0' (reliable), when the
CURR_RD_ADDR and CURR_WR_ADDR are not
being updated by the HW.
- When there is a ongoing bus transfer,
CMD_RESP_EC_BUSY is '1' (not reliable), when the
CURR_RD_ADDR or CURR_WR_ADDR are being
updated by the HW.
Note that this update lasts one I2C clock cycle, or two
SPI clock cycles.
1390
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers