Infineon TRAVEO T2G - 4.13.2.2 CM4_DWT_CYCCNT

Technical Reference Manual 002-29852 Rev. *B
4.13.2.2 CM4_DWT_CYCCNT
Description:
Cycle Count register
Address:
0xE0001004
Offset:
0x4
Retention:
Retained
IsDeepSleep:
No
Comment:
The CYCCNT register characteristics are:
Purpose: Shows or sets the value of the processor cycle counter, CYCCNT.
Usage constraints: The DWT unit suspends CYCCNT counting when the processor is in
Debug state.
Configurations:
Implemented only when CTRL.NOCYCCNT is RAZ, see Control register, CTRL on page C1-
797.
When CTRL.NOCYCCNT is RAO no cycle counter is implemented and this register is
UNK/SBZP.
Attributes: See Table C1-21 on Arm TRM page C1-797.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name CYCNT [7:0]
Bits 15 14 13 12 11 10 9 8
Name CYCNT [15:8]
Bits 23 22 21 20 19 18 17 16
Name CYCNT [23:16]
Bits 31 30 29 28 27 26 25 24
Name CYCNT [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 CYCNT RW RW 0 Incrementing cycle counter value. When enabled,
CYCCNT increments on each processor clock cycle.
On overflow, CYCCNT wraps to zero.
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2022-04-18
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