Infineon TRAVEO T2G - 5.1.17 CPUSS_CM0_CLOCK_CTL

Technical Reference Manual 002-29852 Rev. *B
5.1.17 CPUSS_CM0_CLOCK_CTL
Description:
CM0+ clock control
Address:
0x40201008
Offset:
0x1008
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:0]
Bits 15 14 13 12 11 10 9 8
Name SLOW_INT_DIV [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name PERI_INT_DIV [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
8:15 SLOW_INT_DIV RW R 0 Specifies the slow clock divider (from the peripheral
clock 'clk_peri' to the slow clock 'clk_slow'). Integer
division by (1+SLOW_INT_DIV). Allows for integer
divisions in the range [1, 256] (SLOW_INT_DIV is in
the range [0, 255]).
Note that this field is retained. However, the counter
that is used to implement the division is not and will be
initialized by HW to '0' when transitioning from
DeepSleep to Active power mode.
24:31 PERI_INT_DIV RW R 0 Specifies the peripheral clock divider (from the high
frequency clock 'clk_hf' to the peripheral clock
'clk_peri'). Integer division by (1+PERI_INT_DIV).
Allows for integer divisions in the range [1, 256]
(PERI_INT_DIV is in the range [0, 255]).
Note that this field is retained. However, the counter
that is used to implement the division is not and will be
initialized by HW to '0' when transitioning from
DeepSleep to Active power mode.
Note that Fperi <= Fperi_max. Fperi_max is likely to be
smaller than Fhf_max. In other words, if Fhf =
Fhf_max, PERI_INT_DIV should not be set to '0'.
719
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers