Infineon TRAVEO T2G - 2.3.9.6.56 CANFD_CH_TTIE

Technical Reference Manual 002-29852 Rev. *B
2.3.9.6.56 CANFD_CH_TTIE
Description:
TT Interrupt Enable
Address:
0x40520124
Offset:
0x124
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name GTWE [7:7] SWEE [6:6] TTMIE [5:5] RTMIE [4:4] SOGE [3:3] CSME [2:2] SMCE [1:1] SBCE [0:0]
Bits 15 14 13 12 11 10 9 8
Name IWTE
[15:15]
ELCE
[14:14]
SE2E
[13:13]
SE1E
[12:12]
TXOE
[11:11]
TXUE
[10:10]
GTEE [9:9] GTDE [8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:19] CERE
[18:18]
AWE_
[17:17]
WTE
[16:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 SBCE RW R 0 Start of Basic Cycle Interrupt Enable
0= Interrupt Disabled
1= Interrupt Enabled
1 SMCE RW R 0 Start of Matrix Cycle Interrupt Enable
0= Interrupt Disabled
1= Interrupt Enabled
2 CSME RW R 0 Change of Synchronization Mode Interrupt Enable
0= Interrupt Disabled
1= Interrupt Enabled
3 SOGE RW R 0 Start of Gap Interrupt Enable
0= Interrupt Disabled
1= Interrupt Enabled
4 RTMIE RW R 0 Register Time Mark Interrupt Enable
0= Interrupt Disabled
1= Interrupt Enabled
5 TTMIE RW R 0 Trigger Time Mark Event Internal Enable
0= Interrupt Disabled
1= Interrupt Enabled
6 SWEE RW R 0 Stop Watch Event Interrupt Enable
0= Interrupt Disabled
1= Interrupt Enabled
7 GTWE RW R 0 Global Time Wrap Interrupt Enable
0= Interrupt Disabled
1= Interrupt Enabled
8 GTDE RW R 0 Global Time Discontinuity Interrupt Enable
0= Interrupt Disabled
1= Interrupt Enabled
9 GTEE RW R 0 Global Time Error Interrupt Enable
0= Interrupt Disabled
1= Interrupt Enabled
10 TXUE RW R 0 Tx Count Underflow Interrupt Enable
0= Interrupt Disabled
1= Interrupt Enabled
116
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers