Infineon TRAVEO T2G - 2.3.9.6.27 CANFD_CH_RXF0 S

Technical Reference Manual 002-29852 Rev. *B
2.3.9.6.27 CANFD_CH_RXF0S
Description:
Rx FIFO 0 Status
Address:
0x405200A4
Offset:
0xA4
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:7] F0FL [6:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:14] F0GI [13:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:22] F0PI [21:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:26] RF0L
[25:25]
F0F [24:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:6 F0FL R RW 0 Rx FIFO 0 Fill Level
Number of elements stored in Rx FIFO 0, range 0 to
64.
8:13 F0GI R RW 0 Rx FIFO 0 Get Index
Rx FIFO 0 read index pointer, range 0 to 63.
This field is updated by the software writing to
RxF0A.F0AI
16:21 F0PI R RW 0 Rx FIFO 0 Put Index
Rx FIFO 0 write index pointer, range 0 to 63.
24 F0F R RW 0 Rx FIFO 0 Full
0= Rx FIFO 0 not full
1= Rx FIFO 0 full
25 RF0L R RW 0 Rx FIFO 0 Message Lost
This bit is a copy of interrupt flag IR.RF0L. When
IR.RF0L is reset, this bit is also reset.
0= No Rx FIFO 0 message lost
1= Rx FIFO 0 message lost, also set after write
attempt to Rx FIFO 0 of size zero
84
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers