Infineon TRAVEO T2G - 5 CPUSS

Technical Reference Manual 002-29852 Rev. *B
5 CPUSS
Description
CPU subsystem (CPUSS)
Base Address
0x40200000
Size
0x10000
Slave Num
MMIO2 - 0
Register Name
Address Permission Description
CPUSS_IDENTITY
0x40200000 FULL Identity
CPUSS_CM4_STATUS
0x40200004 FULL CM4 status
CPUSS_CM4_CLOCK_CTL
0x40200008 FULL CM4 clock control
CPUSS_CM4_CTL
0x4020000C FULL CM4 control
CPUSS_CM4_INT0_STATUS
0x40200100 FULL CM4 interrupt 0 status
CPUSS_CM4_INT1_STATUS
0x40200104 FULL CM4 interrupt 1 status
CPUSS_CM4_INT2_STATUS
0x40200108 FULL CM4 interrupt 2 status
CPUSS_CM4_INT3_STATUS
0x4020010C FULL CM4 interrupt 3 status
CPUSS_CM4_INT4_STATUS
0x40200110 FULL CM4 interrupt 4 status
CPUSS_CM4_INT5_STATUS
0x40200114 FULL CM4 interrupt 5 status
CPUSS_CM4_INT6_STATUS
0x40200118 FULL CM4 interrupt 6 status
CPUSS_CM4_INT7_STATUS
0x4020011C FULL CM4 interrupt 7 status
CPUSS_CM4_VECTOR_TABLE_BASE
0x40200200 FULL CM4 vector table base
CPUSS_CM4_NMI_CTL0
0x40200240 FULL CM4 NMI control
CPUSS_CM4_NMI_CTL1
0x40200244 FULL CM4 NMI control
CPUSS_CM4_NMI_CTL2
0x40200248 FULL CM4 NMI control
CPUSS_CM4_NMI_CTL3
0x4020024C FULL CM4 NMI control
CPUSS_CM0_CTL
0x40201000 FULL CM0+ control
CPUSS_CM0_STATUS
0x40201004 FULL CM0+ status
CPUSS_CM0_CLOCK_CTL
0x40201008 FULL CM0+ clock control
CPUSS_CM0_INT0_STATUS
0x40201100 FULL CM0+ interrupt 0 status
CPUSS_CM0_INT1_STATUS
0x40201104 FULL CM0+ interrupt 1 status
CPUSS_CM0_INT2_STATUS
0x40201108 FULL CM0+ interrupt 2 status
CPUSS_CM0_INT3_STATUS
0x4020110C FULL CM0+ interrupt 3 status
CPUSS_CM0_INT4_STATUS
0x40201110 FULL CM0+ interrupt 4 status
CPUSS_CM0_INT5_STATUS
0x40201114 FULL CM0+ interrupt 5 status
CPUSS_CM0_INT6_STATUS
0x40201118 FULL CM0+ interrupt 6 status
CPUSS_CM0_INT7_STATUS
0x4020111C FULL CM0+ interrupt 7 status
CPUSS_CM0_VECTOR_TABLE_BASE
0x40201120 FULL CM0+ vector table base
CPUSS_CM0_NMI_CTL0
0x40201140 FULL CM0+ NMI control
CPUSS_CM0_NMI_CTL1
0x40201144 FULL CM0+ NMI control
CPUSS_CM0_NMI_CTL2
0x40201148 FULL CM0+ NMI control
CPUSS_CM0_NMI_CTL3
0x4020114C FULL CM0+ NMI control
CPUSS_CM4_PWR_CTL
0x40201200 FULL CM4 power control
CPUSS_CM4_PWR_DELAY_CTL
0x40201204 FULL CM4 power control
CPUSS_RAM0_CTL0
0x40201300 FULL RAM 0 control
CPUSS_RAM0_STATUS
0x40201304 FULL RAM 0 status
CPUSS_RAM0_PWR_MACRO_CTL0
0x40201340 FULL RAM 0 power control
CPUSS_RAM0_PWR_MACRO_CTL1
0x40201344 FULL RAM 0 power control
CPUSS_RAM0_PWR_MACRO_CTL2
0x40201348 FULL RAM 0 power control
CPUSS_RAM0_PWR_MACRO_CTL3
0x4020134C FULL RAM 0 power control
CPUSS_RAM0_PWR_MACRO_CTL4
0x40201350 FULL RAM 0 power control
CPUSS_RAM0_PWR_MACRO_CTL5
0x40201354 FULL RAM 0 power control
CPUSS_RAM0_PWR_MACRO_CTL6
0x40201358 FULL RAM 0 power control
CPUSS_RAM0_PWR_MACRO_CTL7
0x4020135C FULL RAM 0 power control
CPUSS_RAM1_CTL0
0x40201380 FULL RAM 1 control
CPUSS_RAM1_STATUS
0x40201384 FULL RAM 1 status
CPUSS_RAM1_PWR_CTL
0x40201388 FULL RAM 1 power control
CPUSS_RAM_PWR_DELAY_CTL
0x402013C0 FULL Power up delay used for all SRAM power domains
CPUSS_ROM_CTL
0x402013C4 FULL ROM control
CPUSS_ECC_CTL
0x402013C8 FULL ECC control
CPUSS_PRODUCT_ID
0x40201400 FULL Product identifier and version (same as CoreSight
RomTables)
CPUSS_DP_STATUS
0x40201410 FULL Debug port status
CPUSS_AP_CTL
0x40201414 FULL Access port control
688
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers