Infineon TRAVEO T2G - 14.2.18 FLASHC_CM4_CA_CTL2

Technical Reference Manual 002-29852 Rev. *B
14.2.18 FLASHC_CM4_CA_CTL2
Description:
CM4 cache control
Address:
0x40240488
Offset:
0x488
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x12C
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name PWRUP_DELAY [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:10] PWRUP_DELAY [9:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:9 PWRUP_DELAY RW R 300 Number clock cycles delay needed after power domain
power up
955
2022-04-18
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