Infineon TRAVEO T2G - 3.8.3.7 CM0 P_SCS_ISPR

Technical Reference Manual 002-29852 Rev. *B
3.8.3.7 CM0P_SCS_ISPR
Description:
Interrupt Set-Pending Register
Address:
0xE000E200
Offset:
0x200
Retention:
Retained
IsDeepSleep:
No
Comment:
On writes, sets the status of one or more interrupts to pending. On reads, shows the
pending status of the interrupts.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name SETPEND [7:0]
Bits 15 14 13 12 11 10 9 8
Name SETPEND [15:8]
Bits 23 22 21 20 19 18 17 16
Name SETPEND [23:16]
Bits 31 30 29 28 27 26 25 24
Name SETPEND [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 SETPEND RW1S R 0 Changes the state of one or more interrupts to
pending. Each bit corresponds to the same numbered
interrupt.
168
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