Infineon TRAVEO T2G - 5.1.27 CPUSS_CM0_NMI_CTL

Technical Reference Manual 002-29852 Rev. *B
5.1.27 CPUSS_CM0_NMI_CTL
Description:
CM0+ NMI control
Address:
0x40201140
Offset:
0x1140
Retention:
Retained
IsDeepSleep:
No
Comment:
Note that multiple (four) CM0_NMI_CTL registers exist, allowing for multiple (four) system
interrupts to be connected to the CPU NMI. The four selected system interrupts are logically
OR'd into a single CPU NMI input. The NMI handler may need to investigate all selected
system interrupt sources to identify the source of CPU NMI.
Default:
0x3FF
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name SYSTEM_INT_IDX [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:10] SYSTEM_INT_IDX [9:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:9 SYSTEM_INT_IDX RW R 1023 System interrupt select for CPU NMI. The reset value
('1023') ensures that the CPU NMI is NOT connected
to any system interrupt after DeepSleep reset.
729
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers