Infineon TRAVEO T2G - 26.8.14 PWR_HIBERNATE

Technical Reference Manual 002-29852 Rev. *B
26.8.14 PWR_HIBERNATE
Description:
HIBERNATE Mode Register
Address:
0x40261008
Offset:
0x1008
Retention:
Retained
IsDeepSleep:
No
Comment:
This register controls entry/exit from HIBERNATE power mode. This register is implemented in
the unregulated voltage domain. This register and PWR_HIB_DATA registers are the only
ones that continue to retain information during HIBERNATE mode. Three identical writes are
required to enter HIBERNATE mode. Ensure changes settle after the third write by reading
this register.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name TOKEN [7:0]
Bits 15 14 13 12 11 10 9 8
Name UNLOCK [15:8]
Bits 23 22 21 20 19 18 17 16
Name POLARITY_HIBPIN [23:20] MASK
_HIBWDT
[19:19]
MASK
_HIBA
LARM
[18:18]
FREEZE
[17:17]
None
[16:16]
Bits 31 30 29 28 27 26 25 24
Name HIBERNATE
[31:31]
HIBERNATE
_DISABLE
[30:30]
None [29:28] MASK_HIBPIN [27:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 TOKEN RW A 0 Contains a 8-bit token that is retained through a
HIBERNATE/WAKEUP sequence that can be used by
firmware to differentiate WAKEUP from a general
RESET event. Note that waking up from HIBERNATE
using XRES will reset this register.
8:15 UNLOCK RW A 0 This byte must be set to 0x3A for FREEZE or
HIBERNATE fields to operate. Any other value in this
register will cause FREEZE/HIBERNATE to have no
effect, except as noted in the FREEZE description.
17 FREEZE RW A 0 Firmware sets this bit to freeze the configuration, mode
and state of all GPIOs and SIOs in the system. When
entering HIBERNATE mode, the first write instructs
DEEPSLEEP peripherals that they cannot ignore the
upcoming freeze command. This occurs even in the
illegal condition where UNLOCK is not set. If UNLOCK
and HIBERNATE are properly set, the IOs actually
freeze on the second write. Supply supervision is
disabled during HIBERNATE mode. HIBERNATE
peripherals ignore resets (excluding XRES) while
FREEZE==1.
18 MASK_HIBALARM RW A 0 When set, HIBERNATE will wakeup for a RTC
interrupt
19 MASK_HIBWDT RW A 0 When set, HIBERNATE will wakeup for WDT interrupt
1647
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers