Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
31 PLL_LS_BYPASS RW R 0 Bypass level shifter inside the PLL. Unused, if no PLL
is present in the product.
0: Do not bypass the level shifter. This setting is ok for
all operational modes and vccd target voltage.
1: Bypass the level shifter. This may reduce jitter on
the PLL output clock, but can only be used when vccd
is targeted to 1.1V nominal. Otherwise, it can result in
clock degradation and static current.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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