Technical Reference Manual 002-29852 Rev. *B
18.13.3.12 LIN_CH_INTR_MASKED
Description:
Interrupt masked
Address:
0x405080CC
Offset:
0xCC
Retention:
Not Retained
IsDeepSleep:
No
Comment:
When read, this register reflects a bitwise AND between the INTR and INTR_MASK registers.
This register allows SW to read the status of all mask enabled interrupt causes with a single
load operation, rather than two load operations: one for INTR and one for INTR_MASK. This
simplifies Firmware development. The associated interrupt is active ('1'), when
INTR_MASKED != 0.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:3] TX
_WAKEUP
_DONE
[2:2]
TX
_RESPON
SE_DONE
[1:1]
TX
_HEADER
_DONE
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None
[15:15]
TIMEOUT
[14:14]
RX_NOISE
_DETECT
[13:13]
None
[12:12]
RX
_HEADER
_SYNC
_DONE
[11:11]
RX_BREAK
_WAKEUP
_DONE
[10:10]
RX
_RESPON
SE_DONE
[9:9]
RX
_HEADER
_DONE
[8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:18] TX
_RESPON
SE_BIT
_ERROR
[17:17]
TX
_HEADER
_BIT
_ERROR
[16:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:29] RX
_RESPON
SE
_CHECKSU
M_ERROR
[28:28]
RX
_RESPON
SE_FRAME
_ERROR
[27:27]
RX
_HEADER
_PARITY
_ERROR
[26:26]
RX
_HEADER
_SYNC
_ERROR
[25:25]
RX
_HEADER
_FRAME
_ERROR
[24:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 TX_HEADER_DONE R W 0 Logical AND of corresponding INTR and INTR_MASK
fields.
1 TX_RESPONSE_DONE R W 0 Logical AND of corresponding INTR and INTR_MASK
fields.
2 TX_WAKEUP_DONE R W 0 Logical AND of corresponding INTR and INTR_MASK
fields.
8 RX_HEADER_DONE R W 0 Logical AND of corresponding INTR and INTR_MASK
fields.
9 RX_RESPONSE_DONE R W 0 Logical AND of corresponding INTR and INTR_MASK
fields.
10 RX_BREAK_WAKEUP
_DONE
R W 0 Logical AND of corresponding INTR and INTR_MASK
fields.
11 RX_HEADER_SYNC
_DONE
R W 0 Logical AND of corresponding INTR and INTR_MASK
fields.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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