Infineon TRAVEO T2G - 5.1.54 CPUSS_CM0_SYSTEM_INT_CTL

Technical Reference Manual 002-29852 Rev. *B
5.1.54 CPUSS_CM0_SYSTEM_INT_CTL
Description:
CM0+ system interrupt control
Address:
0x40208000
Offset:
0x8000
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:3] CPU_INT_IDX [2:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name CPU_INT
_VALID
[31:31]
None [30:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:2 CPU_INT_IDX RW R Undefined CPU interrupt index (legal range [0, 7]). This field
specifies to which CPU interrupt the system interrupt is
mapped. E.g., if CPU_INT_IDX is '6', the system
interrupt is mapped to CPU interrupt '6'.
Note: it is possible to map multiple system interrupts to
the same CPU interrupt. It is advised to assign
different priorities to the CPU interrupts and to assign
system interrupts to CPU interrupts accordingly.
31 CPU_INT_VALID RW R 0 Interrupt enable:
'0': Disabled. The system interrupt will NOT be
mapped to any CPU interrupt.
'1': Enabled. The system interrupt is mapped on CPU
interrupt CPU_INT_IDX.
Note: the CPUs have dedicated
XXX_SYSTEM_INT_CTL registers. In other words, the
CPUs can use different CPU interrupts for the same
system interrupt. However, typically only one of the
CPUs will have the ENABLED field of a specific
system interrupt set to '1'.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers