Infineon TRAVEO T2G - Page 757

Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
0:31 TRIM RW R RAM_TRIM
_DEFAULT
For ARM RAMs the bits are defined as follows
[2:0] EMA: Extra Margin Adjustment (0 is the fastest
setting)
[4:3] EMAW: Extra Margin Adjustment for Writes (0 is
the fastest setting)
[7:5] CTL_BIAS: Control the bias circuit in the SRAM
power switches for SRAMC0: 0=OFF, 7=max
Recommended default value: CTL_BIAS=3, EMAW=0,
EMA=2 (RAM_TRIM_DEFAULT=0x0000_0062,
RAM_TRIM_WIDTH=8)
For Synopsys RAMs the bits are defined as follows:
[3:0] Read-Write margin control. This is used for
setting the Read-Write margin. It programs the sense
amplifier differential setting and allows the trade off
between speed and robustness.
- RM[1:0] values control access time and cycle time of
the memory. RM[1:0] = '0' is the slowest possible
mode of operation for the memory. This setting is
required for VDDMIN operation.
- RM[3:2] are factory pins reserved for debug mode
and should be set to '0'.
[4] RME: Read-Write margin enable control. This
selects between the default Read-Write margin setting,
and the external RM[3:0] Read-Write margin setting.
[7:5] WPULSE: Write Assist Pulse to control pulse
width of negative voltage on SRAM bitline.
[9:8] RA: Read Assist control for WL under-drive.
[14:12] WA: Write assist enable control (Active High).
- WA[2:0] Write Assist pins to control negative voltage
on SRAM bitline.
Recommended default value for LP: WA=4, RA=0,
WPULSE=0, RME=1, RM=3
(RAM_TRIM_DEFAULT=0x0000_4013,
RAM_TRIM_WIDTH=15)
Recommended default value for ULP: WA=6, RA=0,
WPULSE=0, RME=1, RM=2
(RAM_TRIM_DEFAULT=0x0000_6012,
RAM_TRIM_WIDTH=15)
757
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers