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Infineon TRAVEO T2G - 7.5.3.4 CXPI_CH_STATUS

Infineon TRAVEO T2G
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Technical Reference Manual 002-29852 Rev. *B
7.5.3.4 CXPI_CH_STATUS
Description:
Status
Address:
0x4051800C
Offset:
0xC
Retention:
Not Retained
IsDeepSleep:
No
Comment:
The register fields are not retained. This is to ensure that they come up as '0' after coming out
of DeepSleep system power mode.
This is a non-retained register; setting CTL0.ENABLED to '0' clears all status fields to '0'.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:5] HEADER
_RE
SPONSE
[4:4]
None [3:2] RETRIES_COUNT [1:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:14] RX_DONE
[13:13]
TX_DONE
[12:12]
None [11:10] RX_BUSY
[9:9]
TX_BUSY
[8:8]
Bits 23 22 21 20 19 18 17 16
Name RX_DATA
_LENGTH
_ERROR
[23:23]
RX
_HEADER
_PARITY
_ERROR
[22:22]
RX_CRC
_ERROR
[21:21]
TX_BIT_ER
ROR
[20:20]
TX
_HEADER
_ARB
_LOST
[19:19]
TIMEOUT
[18:18]
None [17:16]
Bits 31 30 29 28 27 26 25 24
Name None
[31:31]
TX_FRAME
_ERROR
[30:30]
RX_FRAME
_ERROR
[29:29]
TX
_UNDERF
LOW
_ERROR
[28:28]
RX
_UNDERF
LOW
_ERROR
[27:27]
TX
_OVERFL
OW
_ERROR
[26:26]
RX
_OVERFL
OW
_ERROR
[25:25]
TX_DATA
_LENGTH
_ERROR
[24:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:1 RETRIES_COUNT R W 0 Retries count.
The value reflects the number of retries that HW tries
to transmit a header/response.
HW will reset counter (either case below):
1. after successfully transmit the retry attempt
2. SW clears the CMD.TX_HEADER='0'
3. HW clearing CMD.TX_HEADER=0 due to errors
(TX_BIT_ERROR, TX_HEADER_ARB_LOST,
TX_OVERFLOW_ERROR,
TX_UNDERFLOW_ERROR,
TX_DATA_LENGTH_ERROR, and
TX_FRAME_ERROR)
4 HEADER_RESPONSE R W 0 Frame header/response identifier (only valid when
TX_BUSY or RX_BUSY is '1')
'0' - Frame header being transferred.
'1' - Frame response being transferred.
8 TX_BUSY R W 0 Transmitter busy.
- Set to '1' on the start of the following commands:
TX_HEADER, TX_RESPONSE.
- Set to '0' on successful completion of previous
commands or when an error is detected.
773
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers

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