Infineon TRAVEO T2G - 2.3.9.6.55 CANFD_CH_TTIR

Technical Reference Manual 002-29852 Rev. *B
2.3.9.6.55 CANFD_CH_TTIR
Description:
TT Interrupt Register
Address:
0x40520120
Offset:
0x120
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name GTW [7:7] SWE [6:6] TTMI [5:5] RTMI [4:4] SOG [3:3] CSM_ [2:2] SMC [1:1] SBC [0:0]
Bits 15 14 13 12 11 10 9 8
Name IWT [15:15] ELC [14:14] SE2 [13:13] SE1 [12:12] TXO [11:11] TXU [10:10] GTE [9:9] GTD [8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:19] CER [18:18] AW [17:17] WT [16:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 SBC RW1C RW 0 Start of Basic Cycle
0= No Basic Cycle started since bit has been reset
1= Basic Cycle started
1 SMC RW1C RW 0 Start of Matrix Cycle
0= No Matrix Cycle started since bit has been reset
1= Matrix Cycle started
2 CSM_ RW1C RW 0 Change of Synchronization Mode
0= No change in master to slave relation or schedule
synchronization
1= Master to slave relation or schedule
synchronization changed,
also set when TTOST.SPL is reset
3 SOG RW1C RW 0 Start of Gap
0= No reference message seen with Next_is_Gap bit
set
1= Reference message with Next_is_Gap bit set
becomes valid
4 RTMI RW1C RW 0 Register Time Mark Interrupt
Set when time referenced by TTOCN.TMC (cycle,
local, or global) equals TTTMK.TM, independent
of the synchronization state.
0= Time mark not reached
1= Time mark reached
5 TTMI RW1C RW 0 Trigger Time Mark Event Internal
Internal time mark events are configured by trigger
memory element TMIN (see Section 2.4.7). Set
when the trigger memory element becomes active, and
the M_TTCAN is in synchronization state
In_Gap or In_Schedule.
0= Time mark not reached
1= Time mark reached (Level 0: cycle time
TTOCF.IRTO * 0x200)
114
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers