Infineon TRAVEO T2G - 26.8.30 CLK_FLL_CONFIG

Technical Reference Manual 002-29852 Rev. *B
26.8.30 CLK_FLL_CONFIG
Description:
FLL Configuration Register
Address:
0x40261530
Offset:
0x1530
Retention:
Retained
IsDeepSleep:
Yes
Comment:
This register contains frequency lock loop (FLL) configuration. FLL circuit settings should not
be changed while it is a selected clock (connected to logic). This prevents clock glitches that
can crash the logic. Deselect the FLL using .BYPASS_SEL=FLL_REF
Default:
0x1000000
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name FLL_MULT [7:0]
Bits 15 14 13 12 11 10 9 8
Name FLL_MULT [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:18] FLL_MULT [17:16]
Bits 31 30 29 28 27 26 25 24
Name FLL
_ENABLE
[31:31]
None [30:25] FLL
_OUTPUT
_DIV
[24:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:17 FLL_MULT RW R 0 Multiplier to determine CCO frequency in multiples of
the frequency of the selected reference clock (Fref).
Ffll = (FLL_MULT) * (Fref / REFERENCE_DIV) /
(OUTPUT_DIV+1)
24 FLL_OUTPUT_DIV RW R 1 Control bits for Output divider. Set the divide value
before enabling the FLL, and do not change it while
FLL is enabled.
0: no division
1: divide by 2
1670
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers