Infineon TRAVEO T2G - 9.2.1.4 CH_STRUCT 3; 9.2.1.5 CH_STRUCT 4; 9.2.1.6 CH_STRUCT 5; 9.2.1.7 CH_STRUCT 6

Technical Reference Manual 002-29852 Rev. *B
9.2.1.4 CH_STRUCT 3
Register Name Address Permission Description
DW1_CH_STRUCT3_CH_CTL
0x402980C0 FULL Channel control
DW1_CH_STRUCT3_CH_STATUS
0x402980C4 FULL Channel status
DW1_CH_STRUCT3_CH_IDX
0x402980C8 FULL Channel current indices
DW1_CH_STRUCT3_CH_CURR_PTR
0x402980CC FULL Channel current descriptor pointer
DW1_CH_STRUCT3_INTR
0x402980D0 FULL Interrupt
DW1_CH_STRUCT3_INTR_SET
0x402980D4 FULL Interrupt set
DW1_CH_STRUCT3_INTR_MASK
0x402980D8 FULL Interrupt mask
DW1_CH_STRUCT3_INTR_MASKED
0x402980DC FULL Interrupt masked
DW1_CH_STRUCT3_SRAM_DATA0
0x402980E0 FULL SRAM data 0
DW1_CH_STRUCT3_SRAM_DATA1
0x402980E4 FULL SRAM data 1
DW1_CH_STRUCT3_TR_CMD
0x402980E8 FULL Channel software trigger
9.2.1.5 CH_STRUCT 4
Register Name Address Permission Description
DW1_CH_STRUCT4_CH_CTL
0x40298100 FULL Channel control
DW1_CH_STRUCT4_CH_STATUS
0x40298104 FULL Channel status
DW1_CH_STRUCT4_CH_IDX
0x40298108 FULL Channel current indices
DW1_CH_STRUCT4_CH_CURR_PTR
0x4029810C FULL Channel current descriptor pointer
DW1_CH_STRUCT4_INTR
0x40298110 FULL Interrupt
DW1_CH_STRUCT4_INTR_SET
0x40298114 FULL Interrupt set
DW1_CH_STRUCT4_INTR_MASK
0x40298118 FULL Interrupt mask
DW1_CH_STRUCT4_INTR_MASKED
0x4029811C FULL Interrupt masked
DW1_CH_STRUCT4_SRAM_DATA0
0x40298120 FULL SRAM data 0
DW1_CH_STRUCT4_SRAM_DATA1
0x40298124 FULL SRAM data 1
DW1_CH_STRUCT4_TR_CMD
0x40298128 FULL Channel software trigger
9.2.1.6 CH_STRUCT 5
Register Name Address Permission Description
DW1_CH_STRUCT5_CH_CTL
0x40298140 FULL Channel control
DW1_CH_STRUCT5_CH_STATUS
0x40298144 FULL Channel status
DW1_CH_STRUCT5_CH_IDX
0x40298148 FULL Channel current indices
DW1_CH_STRUCT5_CH_CURR_PTR
0x4029814C FULL Channel current descriptor pointer
DW1_CH_STRUCT5_INTR
0x40298150 FULL Interrupt
DW1_CH_STRUCT5_INTR_SET
0x40298154 FULL Interrupt set
DW1_CH_STRUCT5_INTR_MASK
0x40298158 FULL Interrupt mask
DW1_CH_STRUCT5_INTR_MASKED
0x4029815C FULL Interrupt masked
DW1_CH_STRUCT5_SRAM_DATA0
0x40298160 FULL SRAM data 0
DW1_CH_STRUCT5_SRAM_DATA1
0x40298164 FULL SRAM data 1
DW1_CH_STRUCT5_TR_CMD
0x40298168 FULL Channel software trigger
9.2.1.7 CH_STRUCT 6
Register Name Address Permission Description
DW1_CH_STRUCT6_CH_CTL
0x40298180 FULL Channel control
DW1_CH_STRUCT6_CH_STATUS
0x40298184 FULL Channel status
DW1_CH_STRUCT6_CH_IDX
0x40298188 FULL Channel current indices
DW1_CH_STRUCT6_CH_CURR_PTR
0x4029818C FULL Channel current descriptor pointer
DW1_CH_STRUCT6_INTR
0x40298190 FULL Interrupt
DW1_CH_STRUCT6_INTR_SET
0x40298194 FULL Interrupt set
DW1_CH_STRUCT6_INTR_MASK
0x40298198 FULL Interrupt mask
DW1_CH_STRUCT6_INTR_MASKED
0x4029819C FULL Interrupt masked
DW1_CH_STRUCT6_SRAM_DATA0
0x402981A0 FULL SRAM data 0
DW1_CH_STRUCT6_SRAM_DATA1
0x402981A4 FULL SRAM data 1
DW1_CH_STRUCT6_TR_CMD
0x402981A8 FULL Channel software trigger
9.2.1.8 CH_STRUCT 7
Register Name Address Permission Description
DW1_CH_STRUCT7_CH_CTL
0x402981C0 FULL Channel control
DW1_CH_STRUCT7_CH_STATUS
0x402981C4 FULL Channel status
DW1_CH_STRUCT7_CH_IDX
0x402981C8 FULL Channel current indices
DW1_CH_STRUCT7_CH_CURR_PTR
0x402981CC FULL Channel current descriptor pointer
DW1_CH_STRUCT7_INTR
0x402981D0 FULL Interrupt
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