Infineon TRAVEO T2G - 4.13.2.6 CM4_DWT_LSUCNT

Technical Reference Manual 002-29852 Rev. *B
4.13.2.6 CM4_DWT_LSUCNT
Description:
LSU Count register
Address:
0xE0001014
Offset:
0x14
Retention:
Retained
IsDeepSleep:
No
Comment:
The LSUCNT register characteristics are:
Purpose: Increments on the additional cycles required to execute all load or store instructions
Usage constraints: The counter initializes to 0 when software enables its counter overflow
event by setting the CTRL.LSUEVTENA bit to 1.
Configurations:
Implemented only when CTRL.NOPRFCNT is RAZ, see Control register, CTRL on page C1-
797.
If CTRL.NOPRFCNT is RAO, indicating that the implementation does not include the profiling
counters, this register is UNK/SBZP.
Attributes: See Table C1-21 on Arm TRM page C1-797.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name LSUCNT [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 LSUCNT RW RW 0 Load-store overhead counter. Counts one on each
cycle when all of the following are true:
- No instruction is executed, see CPI Count register,
DWT_CPICNT on page C1-801.
- No exception-entry or exception-exit operation is in
progress, see Exception Overhead Count register,
DWT_EXCCNT on Arm TRM page C1-802.
- A load-store operation is in progress.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers