Technical Reference Manual 002-29852 Rev. *B
26.8.50.6 MCWDT_SERVICE
Description:
MCWDT Service Register
Address:
0x40268094
Offset:
0x94
Retention:
Retained
IsDeepSleep:
Yes
Comment:
Control the behavior of the Watchdog counters. Writes to this register are ignored when
LOCK.MCWDT_LOCK<>0. All fields in this register can be used while counter is in operation.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:2] CTR1
_SERVICE
[1:1]
CTR0
_SERVICE
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 CTR0_SERVICE RW1S RW1C 0 Services subcounter 0. This resets the count value for
subcounter 0 to zero. This may take up to three clk_lf
cycles to take effect. Hardware clears this bit, after
necessary synchronization. To ensure a pending
CTR0_SERVICE write is reflected, firmware should
wait until this bit reads low before attempting to write
CTR0_SERVICE=1. If subcounter 0 is disabled,
CTR0_SERVICE will not trigger a LOWER_ACTION
and will not clear a preloaded count value.
1 CTR1_SERVICE RW1S RW1C 0 Services subcounter 1. This resets the count value for
subcounter 1 to zero. This may take up to three clk_lf
cycles to take effect. Hardware clears this bit, after
necessary synchronization. To ensure a pending
CTR1_SERVICE write is reflected, firmware should
wait until this bit reads low before attempting to write
CTR1_SERVICE=1. If subcounter 1 is disabled,
CTR1_SERVICE will not trigger a LOWER_ACTION
and will not clear a preloaded count value.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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