Technical Reference Manual 002-29852 Rev. *B
Register Name Address Permission Description
DW0_CH_STRUCT51_TR_CMD
0x40288CE8 FULL Channel software trigger
9.1.1.53 CH_STRUCT 52
Register Name Address Permission Description
DW0_CH_STRUCT52_CH_CTL
0x40288D00 FULL Channel control
DW0_CH_STRUCT52_CH_STATUS
0x40288D04 FULL Channel status
DW0_CH_STRUCT52_CH_IDX
0x40288D08 FULL Channel current indices
DW0_CH_STRUCT52_CH_CURR_PTR
0x40288D0C FULL Channel current descriptor pointer
DW0_CH_STRUCT52_INTR
0x40288D10 FULL Interrupt
DW0_CH_STRUCT52_INTR_SET
0x40288D14 FULL Interrupt set
DW0_CH_STRUCT52_INTR_MASK
0x40288D18 FULL Interrupt mask
DW0_CH_STRUCT52_INTR_MASKED
0x40288D1C FULL Interrupt masked
DW0_CH_STRUCT52_SRAM_DATA0
0x40288D20 FULL SRAM data 0
DW0_CH_STRUCT52_SRAM_DATA1
0x40288D24 FULL SRAM data 1
DW0_CH_STRUCT52_TR_CMD
0x40288D28 FULL Channel software trigger
9.1.1.54 CH_STRUCT 53
Register Name Address Permission Description
DW0_CH_STRUCT53_CH_CTL
0x40288D40 FULL Channel control
DW0_CH_STRUCT53_CH_STATUS
0x40288D44 FULL Channel status
DW0_CH_STRUCT53_CH_IDX
0x40288D48 FULL Channel current indices
DW0_CH_STRUCT53_CH_CURR_PTR
0x40288D4C FULL Channel current descriptor pointer
DW0_CH_STRUCT53_INTR
0x40288D50 FULL Interrupt
DW0_CH_STRUCT53_INTR_SET
0x40288D54 FULL Interrupt set
DW0_CH_STRUCT53_INTR_MASK
0x40288D58 FULL Interrupt mask
DW0_CH_STRUCT53_INTR_MASKED
0x40288D5C FULL Interrupt masked
DW0_CH_STRUCT53_SRAM_DATA0
0x40288D60 FULL SRAM data 0
DW0_CH_STRUCT53_SRAM_DATA1
0x40288D64 FULL SRAM data 1
DW0_CH_STRUCT53_TR_CMD
0x40288D68 FULL Channel software trigger
9.1.1.55 CH_STRUCT 54
Register Name Address Permission Description
DW0_CH_STRUCT54_CH_CTL
0x40288D80 FULL Channel control
DW0_CH_STRUCT54_CH_STATUS
0x40288D84 FULL Channel status
DW0_CH_STRUCT54_CH_IDX
0x40288D88 FULL Channel current indices
DW0_CH_STRUCT54_CH_CURR_PTR
0x40288D8C FULL Channel current descriptor pointer
DW0_CH_STRUCT54_INTR
0x40288D90 FULL Interrupt
DW0_CH_STRUCT54_INTR_SET
0x40288D94 FULL Interrupt set
DW0_CH_STRUCT54_INTR_MASK
0x40288D98 FULL Interrupt mask
DW0_CH_STRUCT54_INTR_MASKED
0x40288D9C FULL Interrupt masked
DW0_CH_STRUCT54_SRAM_DATA0
0x40288DA0 FULL SRAM data 0
DW0_CH_STRUCT54_SRAM_DATA1
0x40288DA4 FULL SRAM data 1
DW0_CH_STRUCT54_TR_CMD
0x40288DA8 FULL Channel software trigger
9.1.1.56 CH_STRUCT 55
Register Name Address Permission Description
DW0_CH_STRUCT55_CH_CTL
0x40288DC0 FULL Channel control
DW0_CH_STRUCT55_CH_STATUS
0x40288DC4 FULL Channel status
DW0_CH_STRUCT55_CH_IDX
0x40288DC8 FULL Channel current indices
DW0_CH_STRUCT55_CH_CURR_PTR
0x40288DCC FULL Channel current descriptor pointer
DW0_CH_STRUCT55_INTR
0x40288DD0 FULL Interrupt
DW0_CH_STRUCT55_INTR_SET
0x40288DD4 FULL Interrupt set
DW0_CH_STRUCT55_INTR_MASK
0x40288DD8 FULL Interrupt mask
DW0_CH_STRUCT55_INTR_MASKED
0x40288DDC FULL Interrupt masked
DW0_CH_STRUCT55_SRAM_DATA0
0x40288DE0 FULL SRAM data 0
DW0_CH_STRUCT55_SRAM_DATA1
0x40288DE4 FULL SRAM data 1
DW0_CH_STRUCT55_TR_CMD
0x40288DE8 FULL Channel software trigger
9.1.1.57 CH_STRUCT 56
Register Name Address Permission Description
DW0_CH_STRUCT56_CH_CTL
0x40288E00 FULL Channel control
DW0_CH_STRUCT56_CH_STATUS
0x40288E04 FULL Channel status
DW0_CH_STRUCT56_CH_IDX
0x40288E08 FULL Channel current indices
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers