Infineon TRAVEO T2G - 26.8.36 CLK_PLL_CONFIG

Technical Reference Manual 002-29852 Rev. *B
26.8.36 CLK_PLL_CONFIG
Description:
PLL Configuration Register
Address:
0x40261600
Offset:
0x1600
Retention:
Retained
IsDeepSleep:
Yes
Comment:
This register contains PLL configuration. There is a copy of this register for each PLL. PLL
circuit settings should not be changed while it is a selected clock (connected to logic). This
prevents clock glitches that can crash the logic.
Default:
0x20116
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:7] FEEDBACK_DIV [6:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:13] REFERENCE_DIV [12:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:21] OUTPUT_DIV [20:16]
Bits 31 30 29 28 27 26 25 24
Name ENABLE
[31:31]
None
[30:30]
BYPASS_SEL [29:28] PLL_LF
_MODE
[27:27]
LOCK_DELAY [26:25] None
[24:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0:6 FEEDBACK_DIV RW R 22 Control bits for feedback divider. Set the divide value
before enabling the PLL, and do not change it while
PLL is enabled.
0-21: illegal (undefined behavior)
22: divide by 22
...
112: divide by 112
>112: illegal (undefined behavior)
8:12 REFERENCE_DIV RW R 1 Control bits for reference divider. Set the divide value
before enabling the PLL, and do not change it while
PLL is enabled.
0: illegal (undefined behavior)
1: divide by 1
...
20: divide by 20
others: illegal (undefined behavior)
16:20 OUTPUT_DIV RW R 2 Control bits for Output divider. Set the divide value
before enabling the PLL, and do not change it while
PLL is enabled.
0: illegal (undefined behavior)
1: illegal (undefined behavior)
2: divide by 2. Suitable for direct usage as HFCLK
source.
...
16: divide by 16. Suitable for direct usage as HFCLK
source.
>16: illegal (undefined behavior)
1679
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers