Infineon TRAVEO T2G - 19.5 Register Details; 19.5.1 SAR; 19.5.1.1 PASS_SAR_CTL

Technical Reference Manual 002-29852 Rev. *B
19.5 Register Details
19.5.1 SAR
19.5.1.1 PASS_SAR_CTL
Description:
Analog control register.
Address:
0x40900000
Offset:
0x0
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name PWRUP_TIME [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:11] HALF_LSB
[10:10]
MSB
_STRETCH
[9:9]
IDLE
_PWRDWN
[8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name ENABLED
[31:31]
ADC_EN
[30:30]
SARMUX
_EN [29:29]
None [28:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 PWRUP_TIME RW R 0 Number cycles to wait to power up after
IDLE_PWRDWN.
Check the STATUS.PWRUP_BUSY flag to see if the
delay is still in progress.
The power up delay is 1 us.
8 IDLE_PWRDWN RW R 0 When idle automatically power down the analog.
After an automatic power down a new trigger will
power up the analog, however it will take
PWRUP_TIME cycles before the first acquisition can
be started. Note that re-arbitration happens at that
time, i.e. the trigger that caused the power up may not
get handled first.
9 MSB_STRETCH RW R 0 When set use 2 cycles for the Most Significant Bit
(MSB)
- 0: Use 1 clock cycle for MSB
- 1: Use 2 clock cycles for MSB
10 HALF_LSB RW R 0 When set take an extra cycle to convert the half LSB
and add it to 12-bit result for Missing Code Recovery
This bit should always be set to '1'
- 0: disable half LSB conversion (not recommended)
- 1: enable half LSB conversion
29 SARMUX_EN RW R 0 Enable the SARMUX (only valid if ENABLED=1)
- 0: SARMUX disabled (put analog in power down)
- 1: SARMUX enabled.
1089
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers