Infineon TRAVEO T2G - 15.25.7.10 GPIO_PRT_INTR_CFG

Technical Reference Manual 002-29852 Rev. *B
15.25.7.10 GPIO_PRT_INTR_CFG
Description:
Port interrupt configuration register
Address:
0x40310040
Offset:
0x40
Retention:
Retained
IsDeepSleep:
No
Comment:
This register selects the edge detection type for each pin interrupt.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name EDGE3_SEL [7:6] EDGE2_SEL [5:4] EDGE1_SEL [3:2] EDGE0_SEL [1:0]
Bits 15 14 13 12 11 10 9 8
Name EDGE7_SEL [15:14] EDGE6_SEL [13:12] EDGE5_SEL [11:10] EDGE4_SEL [9:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:21] FLT_SEL [20:18] FLT_EDGE_SEL [17:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:1 EDGE0_SEL RW R 0 Sets which edge will trigger an IRQ for IO pin 0
DISABLE 0 Disabled
RISING 1 Rising edge
FALLING 2 Falling edge
BOTH 3 Both rising and falling edges
2:3 EDGE1_SEL RW R 0 Sets which edge will trigger an IRQ for IO pin 1
4:5 EDGE2_SEL RW R 0 Sets which edge will trigger an IRQ for IO pin 2
6:7 EDGE3_SEL RW R 0 Sets which edge will trigger an IRQ for IO pin 3
8:9 EDGE4_SEL RW R 0 Sets which edge will trigger an IRQ for IO pin 4
10:11 EDGE5_SEL RW R 0 Sets which edge will trigger an IRQ for IO pin 5
12:13 EDGE6_SEL RW R 0 Sets which edge will trigger an IRQ for IO pin 6
14:15 EDGE7_SEL RW R 0 Sets which edge will trigger an IRQ for IO pin 7
16:17 FLT_EDGE_SEL RW R 0 Sets which edge will trigger an IRQ for the glitch
filtered pin (selected by INTR_CFG.FLT_SEL
DISABLE 0 Disabled
RISING 1 Rising edge
FALLING 2 Falling edge
BOTH 3 Both rising and falling edges
18:20 FLT_SEL RW R 0 Selects which pin is routed through the 50ns glitch
filter to provide a glitch-safe interrupt.
1005
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers