Infineon TRAVEO T2G - 5.1.21 CPUSS_CM0_INT3_STATUS

Technical Reference Manual 002-29852 Rev. *B
5.1.21 CPUSS_CM0_INT3_STATUS
Description:
CM0+ interrupt 3 status
Address:
0x4020110C
Offset:
0x110C
Retention:
Not Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name SYSTEM_INT_IDX [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:10] SYSTEM_INT_IDX [9:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name SYSTEM
_INT
_VALID
[31:31]
None [30:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0:9 SYSTEM_INT_IDX R W Undefined Lowest CM0+ activated system interrupt index for CPU
interrupt 3.
See description of CM0_INT0_STATUS.
31 SYSTEM_INT_VALID R W 0 See description of CM0_INT0_STATUS.
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2022-04-18
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