Infineon TRAVEO T2G - 21.504.2.10 PERI_MS_PPU_FX_MS_ATT1

Technical Reference Manual 002-29852 Rev. *B
21.504.2.10 PERI_MS_PPU_FX_MS_ATT1
Description:
Master attributes 1
Address:
0x40010834
Offset:
0x34
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x1F1F1F1F
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:5] PC4_NS
[4:4]
PC4_PW
[3:3]
PC4_PR
[2:2]
PC4_UW
[1:1]
PC4_UR
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:13] PC5_NS
[12:12]
PC5_PW
[11:11]
PC5_PR
[10:10]
PC5_UW
[9:9]
PC5_UR
[8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:21] PC6_NS
[20:20]
PC6_PW
[19:19]
PC6_PR
[18:18]
PC6_UW
[17:17]
PC6_UR
[16:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:29] PC7_NS
[28:28]
PC7_PW
[27:27]
PC7_PR
[26:26]
PC7_UW
[25:25]
PC7_UR
[24:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 PC4_UR R R 1 Protection context 4, user read enable.
1 PC4_UW RW R 1 Protection context 4, user write enable.
2 PC4_PR R R 1 Protection context 4, privileged read enable.
3 PC4_PW RW R 1 Protection context 4, privileged write enable.
4 PC4_NS RW R 1 Protection context 4, non-secure.
8 PC5_UR R R 1 Protection context 5, user read enable.
9 PC5_UW RW R 1 Protection context 5, user write enable.
10 PC5_PR R R 1 Protection context 5, privileged read enable.
11 PC5_PW RW R 1 Protection context 5, privileged write enable.
12 PC5_NS RW R 1 Protection context 5, non-secure.
16 PC6_UR R R 1 Protection context 6, user read enable.
17 PC6_UW RW R 1 Protection context 6, user write enable.
18 PC6_PR R R 1 Protection context 6, privileged read enable.
19 PC6_PW RW R 1 Protection context 6, privileged write enable.
20 PC6_NS RW R 1 Protection context 6, non-secure.
24 PC7_UR R R 1 Protection context 7, user read enable.
25 PC7_UW RW R 1 Protection context 7, user write enable.
26 PC7_PR R R 1 Protection context 7, privileged read enable.
27 PC7_PW RW R 1 Protection context 7, privileged write enable.
28 PC7_NS RW R 1 Protection context 7, non-secure.
1307
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers